JP2010000716A - Electronic controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic controller operable while restraining an electric power consumption, in the electronic controller for computation-processing a required image data. <P>SOLUTION: This electronic controller has a peripheral circuit, the first control element (the first CPU 16) operated by a prescribed electric power consumption to control the peripheral circuit, the second control element (the second CPU 17) operated by the electric power consumption smaller than the prescribed electric power consumption of the first control element, to control the peripheral circuit, and a change over control circuit 12 for controlling the peripheral circuit by the first control element at the time of usual condition, and for stopping an operation of the first control element at the time of standby condition, to control the peripheral circuit by the second control element, and the electronic controller is operable while restraining the electric power consumption. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an electronic control device including a control element for controlling a predetermined peripheral circuit.

  When an image is drawn on a memory and processed, predetermined image processing is usually performed by a processing device such as a CPU. For example, in a device such as a commercially available printer, for drawing processing of an image to be printed, A single CPU is used to draw objects one by one on the band memory in order. In addition, it is known as an apparatus that performs an operation by performing parallel processing using a plurality of CPUs instead of a single CPU for image data for one page or one screen (see, for example, Patent Document 1).

  In such an apparatus that performs arithmetic processing by performing parallel processing using a plurality of CPUs, an SMP (Symmetric Multi-Processor) configuration is adopted, and execution of program tasks is scheduled with priority, and is executed on each CPU. Multiple program tasks are executed simultaneously in parallel. Compared to processing with a single CPU, the throughput of the entire apparatus can be increased, and high-speed processing can be realized.

Japanese Patent Laid-Open No. 2001-287412

  In the above-described apparatus that performs arithmetic processing by performing parallel processing using a plurality of CPUs, high-speed processing by parallel processing is realized for very large image data. However, when parallel processing is performed using a plurality of CPUs, power consumption also increases in accordance with the number of CPUs. For example, in a printing apparatus such as a printer, in a normal operation state and a standby state, Since the required power is also different, the design based on the normal operation cannot realize sufficient power saving. In addition, there are devices that can switch between the standby power saving mode and the normal mode even in the CPU itself. However, when a high-speed CPU with high processing capability corresponding to high-speed data processing is adopted, power saving for standby is possible. Even in the operation in the mode, the power consumption is only low compared to the high power consumption state in the normal mode, and it is difficult to say that the system has sufficiently low power consumption.

  In view of the above technical problem, an object of the present invention is to provide an electronic control device that can operate while suppressing power consumption in an electronic control device that performs arithmetic processing on required image data.

  In order to solve the above technical problem, an electronic control device of the present invention includes a peripheral circuit, a first control element that operates with a predetermined power consumption and controls the peripheral circuit, and the first control element. A second control element that operates with a power consumption smaller than the power consumption and controls the peripheral circuit; and the peripheral circuit is controlled by the first control element in a normal state and the first control element in a standby state. And a switching control section for stopping the operation of one control element and controlling the peripheral circuit by the second control element.

  By selectively using the control elements having two different power consumptions, the operation of the control elements having a large power consumption can be stopped in the standby state, and the overall power consumption can be suppressed. In a normal operation state, even if the power consumption is large, the control element on the higher performance side can be operated, and the performance is not reduced due to power saving.

[First embodiment]
A preferred embodiment of an image forming apparatus using an electronic control device of the present invention will be described with reference to the drawings. The image forming apparatus of the present embodiment is an example of a printing apparatus that performs printing, and constructs a printing system as shown in FIG.

  As shown in FIG. 1, user computers 1 to 3 used by a plurality of users and an image forming apparatus 4 are connected by a network. For example, when the user operates the user personal computer 1 and issues a print command, the image forming apparatus 4 shared with the other user personal computers 2 and 3 executes printing based on the command from the user personal computer 1. can do.

  FIG. 2 is a block diagram showing a configuration of the image forming apparatus 4. The image forming apparatus 4 has a network interface, temporarily stores data sent from the user personal computers 1 to 3 in the RAM 24, analyzes it by the CPU, develops it into raster data, and prints it by the image forming means 21 described later. is there.

  A network interface control unit 11 is connected to a network communication line 10 for connecting the image forming apparatus 4 and the user personal computers 1 to 3. The network communication line 10 is, for example, a twisted pair line and corresponds to the Ethernet (registered trademark) system. A network communication line 10 connects to an external network. The image forming apparatus 4 is provided with a bus 19, through which the memory control unit 20 is connected to the first CPU (CPU 1) 16 and the second CPU (CPU 2) 17. The first CPU (CPU1) 16 and the second CPU (CPU2) 17 function as a first control element and a second control element.

  Although the details will be described later, the control element switching unit 12 has a function of selecting the first control element, the first CPU 16 as the second control element, and the second CPU 17 between the normal state and the standby state. . An interrupt signal line 13 is connected from the network interface control unit 11 to each of the CPUs 16 and 17. The signal of the interrupt signal line 13 is received when communication data is received from the outside and the received data is completely stored in the RAM 24. validate.

The CPU1_RESET signal line 14 is a signal line for transmitting a reset signal for stopping the function of the first CPU 16 serving as the first control element from the control element switching unit 12 to the first CPU 16. The reset signal is reset when it is at “L” level, and is not reset when it is at “H” level. Similarly, the CPU2_RESET signal line 15 is a signal line for transmitting a reset signal for stopping the function of the second CPU 17 serving as the second control element from the control element switching unit 12 to the second CPU 17. The content of the signal on the CPU2_RESET signal line 15 is the same as the signal on the CPU1_RESET signal line 14.

  The first CPU 16 is a first control element, and is set to be equivalent to, for example, MPC7447 1420 MHz manufactured by Freescale. In the first CPU 16, the power consumption during normal operation is, for example, 21.0 W on average, and 4.1 W on average during power saving. The first CPU 16 is characterized in that the operation clock is high and the internal cache capacity is large, so that the processing capability is higher than that of the second control element and the power consumption is large. When an “L” level reset signal for resetting is applied to the first CPU 16, the internal clock is stopped and the power consumption becomes approximately 0 W.

  The second CPU 17 is a second control element, and is set to, for example, a product equivalent to PPC750CL, 400 MHz manufactured by IBM. In the second CPU 17, the power consumption during normal operation is, for example, 1.7 W on average, and is about 0.4 W on average during power saving. The CPU 17 has a lower operation clock and less internal cache than the CPU 16 that is the first control element. Therefore, although the CPU 17 has a low processing capacity, it consumes less power and is suitable for monitoring a network during standby. The program instructions to the second CPU 17 are compatible with those of the first CPU 16, and the functions are the same as those of the CPU 16 except for the cache capacity setting and the internal clock setting set in the internal register. It is.

  The ROM_SWITCH signal line 18 transmits a switching signal output from the control element switching unit 12 to the memory control unit 20. The ROM_SWITCH signal is a signal for causing the memory control unit 20 to select either the initial program stored in the ROM 26 or the restart program stored in the RAM 24 when the control element is released from reset and restarted. is there. When the ROM_SWITCH signal is at the “L” level, the memory control unit 20 is made to select the initial program stored in the initial program area 27 on the ROM 26. The memory control unit 20 selects the restart program.

  In the image forming apparatus 4, the bus 19 is a CPU_BUS signal line, and includes, for example, a 32-bit address bus and a 64-bit data bus. The memory control unit 20 connected to the bus 19 accesses the RAM 24 and the ROM 26 corresponding to the addresses designated by the bus 19 from the CPUs 16 and 17. Further, as described above, the memory control unit 20 can switch and control the memory at the time of restart according to the ROM_SWITCH signal from the control element switching unit 12.

  The image forming unit 21 functions as a peripheral circuit controlled by a control element, and includes a photosensitive drum, a print head (LED head), a fixing device, a transfer device, a transport system, and the like (not shown). Connected to the first CPU 16 and the like. The image forming unit 21 can print on paper based on the data processed by the CPU 16.

  For the connection between the memory control unit 20 and the RAM 24 and the ROM 26, a RAM bus 22 for connecting to the RAM 24 and a ROM bus 23 for connecting to the ROM 26 are used. The RAM bus 22 is composed of a 64-bit data bus and a control signal, and the ROM bus 23 is composed of a 64-bit data bus, a 20-bit address bus and a control signal. The RAM 24 is a readable / writable memory device, and can store and execute a program. The restart program area 25 is a storage area for a program developed on the RAM 24, and stores a restart program. The ROM 26 is a memory device that can only be read in normal use. An initial program area 27 of the ROM 26 stores an initial program.

  The first CPU 16 has an internal register 28, and the second CPU 17 has an internal register 29. These internal registers 28 and 29 each function to store a CPU state and setting information, a CPU version, and the like as will be described later. By switching the CPU while reading the information in the internal registers 28 and 29, smooth CPU switching is realized.

  Next, the internal structure of the control element switching unit 12 will be described with reference to FIG. The control element switching unit 12 is a circuit unit that switches and controls the two CPUs 16 and 17, and a command analysis unit 41 is connected to an internal bus 40 for receiving a CPU_BUS signal. Like the bus 19, the internal bus 40 includes a 32-bit address bus and a 64-bit data bus. The command analysis unit 41 decodes a command written from the control element via the internal bus 40 of the CPU_BUS signal and outputs a state switching signal. An ECO_MODE signal line 42 and a NOR_MODE signal line 43 are used for a state switching signal. The ECO_MODE signal line 42 is a signal line that transmits an ECO_MODE signal that is decoded and validated by the command analysis unit 41 when a command to shift to the standby mode is written from the first CPU 16, and the ECO_MODE signal is at the “L” level. Is instructed to shift to the standby state, and is invalid in the case of “H” level. The NOR_MODE signal line 43 is a signal line that transmits a NOR_MODE signal that is decoded and validated by the command analysis unit 41 when a command to shift to the standby mode is written from the second CPU 17, and the NOR_MODE signal is “L”. In the case of the level, the content is instructed to shift to the normal state, and in the case of the “H” level, it is invalid.

  The state machine 44 is a sequential circuit composed of combinational circuits and flip-flops, and the contents are represented by a state transition diagram as shown in FIG. The state is changed by the ECO_MODE signal and the NOR_MODE signal output from the command analysis unit 41, and the CPU1_RESET signal line 14, the CPU2_RESET signal line 15, and the ROM_SWITCH signal line 18 on the output side of the state machine 44 are used. Each signal is output. When the CPU1_RESET signal is at "L" level, the first CPU 16 is reset, and when it is at "H" level, an operation is instructed. When the CPU2_RESET signal is at "L" level, the second CPU 17 is reset, and when it is at "H" level, an operation is instructed. The ROM_SWITCH signal is output to the memory control unit 20 and functions to select either an initial program or a restart program as an initial program of the CPU. For example, when the ROM_SWITCH signal is “L” level, an initial program is instructed, and when the ROM_SWITCH signal is “H” level, a restart program is instructed. The state machine 44 is connected to the reset circuit 48 to monitor the power supply voltage, and the output from the reset circuit 48 is at the “H” level when the power is on, and at the “L” level when the power is off.

  Next, the internal register group 50 held by each of the first CPU 16 and the second CPU 17 will be described with reference to FIG. The internal register group 50 corresponds to the internal registers 28 and 29 in FIG. The internal register group 50 has a common configuration for the first CPU 16 and the second CPU 17, so that data can be smoothly transferred between the first CPU 16 and the second CPU 17.

  General-purpose registers (REG0 to REGn) 51 to 56 are arranged as registers constituting the internal register group 50, and in particular, the register 51 indicated by REG0 is used as a pointer of the heap memory. Further, as registers constituting the internal register group 50, there are a program counter 57, a link register (LR) 58 for storing return addresses such as traps and global jumps, and an offset value for address conversion to the virtual memory space. A memory conversion table register (BAT0) 59 to be stored, a condition register (CR) 60 to store the state of the CPU, a master status register (MSR) 61 to store CPU setting information, and a processor-specific value are stored. A processor version register (PVR) 62 is provided that allows the CPU to determine what the value is.

 Next, the operation of the image forming apparatus of this embodiment will be described. First, the flow from turning on the power to printing will be described with reference to FIG. 7. Next, the CPU switching process will be described with reference to FIG. 10, and then the process when the restart process is performed. This will be described with reference to FIG.

  FIG. 7 is a flowchart from the image forming apparatus according to the embodiment until printing is performed after the power is turned on through a standby state. First, in step 80, the power is turned on, and at this time, either the first CPU 16 or the second CPU 17 is operated. The first CPU 16 and the second CPU 17 are activated according to the power-off timing or the like. It will be uncertain which one will be. In step 81, the processor version register in the operating CPU is read to identify the CPU type. The processor version register (PVR) 62 is a register in which a unique number for identifying the CPU type is stored, and the CPU type is identified by the stored unique number.

  Based on the reading of the unique number from the processor version register (PVR) 62, it is determined whether the first CPU (CPU 1) 16 or the second CPU (CPU 2) 17 is operating (step 82). If the operating CPU is the first CPU (CPU 1) 16, the process proceeds to step 84, and if the operating CPU is the second CPU (CPU 2) 17, the process proceeds to step 86. In step 84, the first CPU (CPU 1) 16 sets a unique register. Specifically, the clock of the first CPU (CPU 1) 16 is set to 1420 MHz. In step 86, the second CPU (CPU 2) 17 sets a unique register. Specifically, the clock of the second CPU (CPU1) 17 is set to 400 MHz.

  When such setting for the CPU is performed, the RAM 24 is checked (step 87). This RAM 24 check is performed if there is data written when the power is turned off. If the stored contents of the RAM 24 are damaged, the same operation as when the power is turned off cannot be performed. If it is broken, specific data may be written. Next, in step 88, the program is read from the ROM 26 and developed in the RAM 24. When an interrupt factor occurs, an interrupt vector, which is a vector for writing the start address where the processing program exists, is written into the RAM. A restart program is also initially stored in the ROM 26, and this restart program is also expanded in the RAM 24. Before and after these steps 87 and 88, the CPU that operates at the time of start-up is controlled to be the first CPU 16 having a high processing capability.

  In step 89, the image forming apparatus 4 is initialized. The image forming apparatus 4 is equipped with a fixing device, and a heater for fusing the toner transferred onto the paper to the paper is built in the fixing device. The heater uses a halogen lamp. Since the heater takes time to reach the temperature required for toner fusion, the temperature of the fixing device starts to rise early. After the initialization of the image forming apparatus 4, the network interface control unit 11 is initialized. In the initialization of the network interface control unit 11, a communication method is determined by setting an address in the network and an auto-negotiation function of the Ethernet (registered trademark) controller.

  Next, it is determined whether or not the fixing device of the image forming apparatus 4 has reached a temperature at which a predetermined fixing operation can be performed (step 91). If not, wait that initialization is still in progress. If the predetermined temperature has been reached, it is determined that initialization has been completed, and the routine proceeds to step 92. In step 92, a power saving transition timer, which is a timer for shifting to the power saving mode, is initialized, and the fixing device is designed to maintain a constant temperature. Further, if printing is not performed for a certain period of time, the power supply of the heater of the fixing device is shut off for power saving, but the power saving transition timer determines this certain period of time. As an example of the power saving transition timer, a time of about 30 minutes is set.

  After setting the power saving transition timer, CPU switching processing is performed. In this CPU switching process, the first CPU 16 switches to the second CPU 17 with low power consumption (step 93). The image forming apparatus 4 enters a standby state from here. That is, since a high processing capacity is not required in the standby state, the second CPU 17 having a lower power consumption than the first CPU 16 is selected. A more specific procedure of the switching process will be described later with reference to FIGS.

  In step 94, standby processing is performed using the second CPU 17 with low power consumption. In this standby process, the network is monitored, the received packet is analyzed, and an inquiry about device information is handled. As the control element in this case, since the second CPU 17 with low power consumption is selectively used, the power consumption of the entire apparatus can be suppressed. If the print data is included in the packet, the standby process is exited. The detailed procedure will be described later with reference to FIG. 8, but the network is monitored, and when the print data is input to the image forming apparatus 4, a transition from the standby process to the normal state is attempted.

  In step 95 after standby processing, CPU switching processing is performed. The control element to be used is switched from the second CPU 17 with low power consumption to the first CPU 16 with high processing capability. From here, the image forming apparatus 4 transitions to the normal state again. In step 96, the image forming apparatus 4 is turned on, and control is started so that the temperature of the fixing device becomes an appropriate temperature. At this time, since the control element is the first CPU 16 having a high processing capability, quick control can be realized even if power saving is achieved in the standby state.

  After the power is turned on for the image forming apparatus 4 in step 96, the image forming apparatus 4 performs reception processing. In this receiving process, print data sent from the user personal computers 1 to 3 is received (step 97). After this reception processing, in step 98, printing processing is performed. During this printing process, raster data is generated from the print data, sent to the print head (LED head), and printing is performed on a predetermined sheet by controlling the photosensitive drum, the fixing device, and the transfer device.

  In the flow from when the image forming apparatus according to the above embodiment is turned on to printing through the standby state, the second CPU 17 having a small power consumption is used as a control element in the standby state, and print data is stored. The longer the time until instructed via the network, the higher the power saving effect.

  Next, a flow when performing CPU switching processing will be described with reference to FIG. First, in step 70, CPU switching processing is started. First, a cache flush is executed (step 71). The cache is a high-speed storage device provided in the CPU, and the flash is to write back the contents of this memory to the RAM 24. Next, the contents of the register are stored in the RAM 24 (step 72). Here, the contents of the register indicate data written in the register group shown in FIG.

  After the contents of the register are stored in the RAM 24, a CPU switching command is written in the control element switching unit 12 (step 73). The CPU switching operation here proceeds as described in FIG. After the CPU switching command is written in the control element switching unit 12, a restart process is performed in step 74. In this restart process, after switching, the CPU is released from the reset and starts operating from an address indicated by a predetermined reset vector. Details of the processing will be described later with reference to FIG. When this restart process is completed, the CPU switching process ends.

  As described above, when the CPU switching process is performed, after the contents of the cache and the register group are stored in the RAM 24 before the CPU is restarted, the process proceeds to the restart process. In the middle of this restart, smooth switching processing of the CPU is performed using the data stored in the RAM 24.

  Next, a flow when performing standby processing will be described with reference to FIG. When the standby process is started in step 100, first, in step 101, it is checked whether there is a reception interruption while monitoring the signal received by the network interface control unit 11. If there is no reception interruption (No), it is determined in step 107 whether or not the power saving time has elapsed. If the power saving time has not elapsed (No), the process returns to the reception interruption step. If the power saving time has elapsed (Yes), the power of the image forming apparatus itself is controlled to be OFF in step 108, and the process returns to the reception interrupt step.

  If there is a reception interruption in Step 101 (Yes), the packet data is transferred to the RAM in Step 102, and then the packet analysis is executed in Step 103. As a result of this packet analysis, it is first determined whether or not the content of the interruption is an inquiry about device information (step 104). If the inquiry is about device information (Yes), predetermined device information is returned at step 109. Return to the reception interrupt step. If it is not an inquiry about device information in step 104 (No), it is determined in step 105 whether or not it is a request for Web data. . If it is not a request for Web data in Step 105 (No), it is determined in Step 106 whether or not it is print data, and if it is not print data (No), the process returns to the reception interruption step. If it is determined that the data received in step 106 is print data (Yes), the standby process is terminated in order to shift to a printing operation.

  In the above-described standby state, the amount of power consumed can be suppressed by using the second CPU with low power consumption. Further, when switching to the normal state by receiving print data, the peripheral circuits of the first CPU and the second CPU are partly in common and the RAM power remains on, so it is necessary to perform a RAM check. Disappears.

  Next, a flow for performing the restart process will be described with reference to FIG. When the restart process is started in step 200, the data stored in the PVR register 62 in the CPU is read in step 201. The PVR register 62 is a register that stores a unique number for identifying the type of CPU. Based on the PVR register 62, it is determined which of the first CPU 16 and the second CPU 17 is operating.

  In step 202, if the result is the first CPU (CPU 1) 16 based on the result of step 201, the process proceeds to step 203. If the second CPU (CPU 2) 17 is used, the process proceeds to step 205. In step 203, each data of the register group 50 stored in the RAM 24 is written into the register 28 of the first CPU (CPU 1) 16. Subsequently, in step 204, a register specific to the first CPU (CPU1) 16 is set, and the clock of the first CPU (CPU1) 16 is set to 1420 MHz. In step 205, each data of the register group 50 stored in the RAM 24 is written in the register 29 of the second CPU (CPU 2) 17. Subsequently, in step 206, a register specific to the second CPU (CPU 2) 17 is set, and the clock of the second CPU (CPU 2) 17 is set to 400 MHz.

  After such CPU setting, the program jumps to the address indicated by the program counter 57 (step 207). After this predetermined address jump, the restart process is terminated (step 208). In this restart process, the data stored in the PVR register 62 is read out, the operating CPU is determined, and each data of the register group 50 stored in the RAM 24 is written to the internal register of the CPU. Perform the startup operation. Therefore, regardless of the operating CPU, a smooth startup operation can be realized without initializing the peripheral circuits.

  Next, the operation in the switching control unit 12 will be described with reference to FIG. FIG. 4 is a state transition diagram of the state machine 44. Reference numeral 30 denotes a reset state S1, and all outputs of the state machine 44 are set to the “L” level. Reference numeral 31 denotes a normal state S2, in order to operate the first CPU 16, the CPU1_RESET signal is at "H" level, the CPU2_RESET signal is at "L" level, and the ROM_SWITCH signal is at "L" level. Reference numeral 32 denotes a standby state S3, which indicates a mode used in the standby state. In order to operate the second CPU 17, the CPU1_RESET signal is "L" level, the CPU2_RESET signal is "H" level, and the ROM_SWITCH signal is " H "level. 33 is the normal state S4. In order to operate the first CPU 16, the CPU1_RESET signal is at "H" level, the CPU2_RESET signal is at "L" level, and the ROM_SWITCH signal is at "H" level.

  The state transition of the state machine 44 will be described with reference to FIG. 4. First, when the image forming apparatus 4 is turned on, the reset Sl state 30 is entered. When the power supply becomes a predetermined voltage and becomes stable, the reset is released and the normal state S2 (state 31) is entered. The reset of the first CPU 16 is released and the initial program is executed to initialize the RAM 24, the network interface control unit 11, and the image forming unit 21.

  When a series of initialization processes are completed, the processing capacity of the first CPU 16 becomes unnecessary and the operation is stopped for power saving. The second CPU 17 is activated in place of the first CPU 16. At this time, the first CPU 16 first stores the information of the internal register 28 in the RAM 24. Next, when the storage is completed, a switching command is written in the control element switching unit 12. When the command is written, the control element switching unit 12 shifts to the standby state S3 (state 32). Then, the first CPU 16 is reset and the operation is stopped. Instead, the second CPU 17 releases the reset and reads the restart program. Since the second CPU 17 takes over the value of the internal register from the first CPU 16 by the restart program, the second CPU 17 resumes the operation from the point where the second CPU 16 stopped without initializing the peripheral circuit.

  The second CPU 17 monitors the network interface control unit 12 in the standby state S3 (state 32). In this monitoring state, the first CPU 16 is restarted when the packet that is always sent is analyzed and data that requires processing capability is found. Data requiring processing capability is called PDL (Page Description Language), and is character data, image data, or the like.

  Regarding the transition from the state 32 to the state 33, the second CPU 17 first stores the information of the internal register 29 in the RAM 24. Next, when the storage is completed, a switching command is written in the control element switching unit 12. When the command is written, the control element switching unit shifts to the normal state S4 (state 33). Then, the second CPU 17 is reset to stop the operation. Instead, the first CPU 16 releases the reset and reads the restart program. Since the CPU 16 takes over the value of the internal register from the second CPU 17 by the restart program, the operation is resumed from the point where the second CPU 17 is stopped without damaging the print data received in the RAM 24.

  FIG. 5 shows changes in the state machine 44 and changes in the signal. For example, in the states S2 and S4 of the state machine, it can be seen that the CPU 1_RESET signal is at the “H” level and the CPU 2_RESET signal is at the “L” level, so that the high-speed processing by the first CPU 16 proceeds. On the other hand, in the state S3, the CPU1_RESET signal is at the “L” level and the CPU2_RESET signal is at the “H” level, and the power saving process by the second CPU 17 is advanced.

  FIG. 6 shows changes in signals when the standby state S3 (state 32) is shifted to the normal state S4 (state 33). For example, in the state S32, the CPU1_RESET signal is at the “L” level and the CPU2_RESET signal is at the “H” level, and the power saving process by the second CPU 17 is in progress. It can be seen that the high-speed processing by the first CPU 16 proceeds when the signal is at the “H” level and the CPU2_RESET signal is at the “L” level. The portion indicated as the state of the control unit indicates that the state a is the state before the interruption, and the state b indicates that the interruption signal INT has the “L” level and an interruption operation has occurred. In the state c shown as the state of the control unit, data is stored from the internal register of the second CPU 17 to the RAM 24, and in the state d, the high-speed processing by the first CPU 16 is advanced.

  Consider the power applied to each CPU 16, 17 as a control element. If one hour of the day is considered a normal state and the remaining 23 hours are assumed to be in a standby state, 1 is used when only the power saving mode of the first CPU is used without switching control. Daily power consumption = 4.1 W × 23 h + 21.0 W × 1 = 115 W. On the other hand, according to the image forming apparatus of the present embodiment, switching control can be performed, and power consumption per day = 0.4 W × 23 h + 21.0 W × 1 = 30.2 W, which is approximately 73% of power saving effect. Will be obtained.

  In addition, according to the present embodiment, the reception performance during normal operation, which has been a concern, is not degraded by the high processing capability of the first CPU 16 itself. Further, according to the present embodiment, when switching to the normal state due to reception of print data in the standby state, a time for RAM check or the like does not occur, so that the reception data holding time can be shortened. Furthermore, according to the present embodiment, the peripheral circuits of the first CPU 16 and the second CPU 17 can be made common, and an advantage that the circuit configuration can be reduced can be obtained.

[Second Embodiment]
In the previous embodiment, since two commercially available CPUs are mounted, there are disadvantages in terms of product price, the area occupied by the CPU on the substrate, etc., and this embodiment is capable of eliminating these points. It is an example of an apparatus.

  FIG. 12 is a block diagram illustrating a configuration example of the image forming apparatus 120 including a CPU built-in memory control unit in which a function equivalent to that of the second CPU is incorporated in the memory control unit. In FIG. 12, the same reference numerals are assigned to the same components as those of the image forming apparatus 4 of the first embodiment shown in FIG.

  The image forming apparatus 120 is an example of a printing apparatus that executes electrophotographic printing, and includes a first CPU 121 as a first control element. The first CPU (CPU1) 121 is equivalent to, for example, PPC970 and 2 GHz manufactured by IBM. The average power consumption of the first CPU (CPU1) 121 during normal operation is 100 W on average, and 22 W on average during power saving. The first CPU (CPU1) 121 is characterized by a high operation clock and a large internal cache capacity, and therefore has a higher processing capacity than a second control element described later and consumes more power. The first CPU (CPU 1) 121 has an internal register 122, and when the CPU is switched, the data stored in the RAM can be read to perform a smooth start-up operation.

  A power supply voltage is supplied to the first CPU (CPU 1) 121 from the power supply circuit 126 for the first CPU (CPU 1) 121 through the power supply line 123, and a reset signal from the reset circuit 125 passes through the reset signal line 124. Supplied through. The reset circuit 125 is a circuit that resets the first CPU 121 when the power to the first CPU 121 is lowered and when a reset signal is output from the control element switching unit 12. The power supply circuit 126 is a DC / DC circuit and has a function capable of shutting off the power supply in accordance with an external reset signal.

  The output from the first CPU (CPU 1) 121 is sent to the bus via the tri-state buffer 127, and when the power of the first CPU 121 is cut off, the leakage current is cut off from the memory control unit 130. Specifically, the tri-state buffer 127 can set the output of a normal buffer to a high impedance according to the level of the control signal, and the output terminal is disconnected from the internal circuit by setting the high impedance. Form an equivalent state.

  In this embodiment, the second CPU (CPU 2) 129 that selectively operates with the first CPU (CPU 1) 121 is equivalent to IBM PPC405, 200 MHz. The second CPU (CPU 2) 129 is made into a hard macro and incorporated in the memory control unit 130. The average power consumption of the second CPU (CPU2) 129 during normal operation is 1 W or less on average, and about 0.1 W on average during power saving. The second CPU (CPU2) 129 has a low operation clock and a small internal cache, and therefore has a low processing capacity. The program instructions are compatible with the first CPU (CPU1) 121, and the functions are the same as those of the first CPU (CPU1) 121 except for the cache capacity setting and the internal clock setting set in the internal register. Since the second CPU 129 is incorporated in the memory control unit 130, it is not necessary to individually mount the second CPU on the substrate, and in the present embodiment, although a plurality of CPUs are selectively operated, The area occupied by the CPU is smaller than that of the image forming apparatus 4 of the first embodiment, which is advantageous in terms of cost. The second CPU (CPU2) 129 has an internal register 128, and when the CPU is switched, the data stored in the RAM can be read to perform a smooth start-up operation.

The memory control unit 130 has the same configuration as the memory control unit 20 of the previous embodiment,
The difference is that the second CPU (CPU 2) 129 is built in and that the operation clock is increased corresponding to the PPC 970. Although the tristate buffer 127 is part of the memory control unit 130, it can be external to the memory control unit 130.

The image forming apparatus 120 of this embodiment having such a configuration is in a reset state when the power is turned on, as in the previous embodiment. When the power supply becomes a predetermined voltage and becomes stable, the reset is released and the normal state is entered. At this time, the reset of the first CPU 121 is canceled and the initial program is executed, and the RAM 24, the network interface control unit 11, and the image forming unit 21 are initialized.

  When these initialization processes are completed, the processing capacity of the first CPU 121 becomes unnecessary and the operation is stopped for power saving. Instead of the first CPU 121, the second CPU 129 is activated. At this time, the first CPU 121 first stores the information of the internal register 122 in the RAM 24. Next, when the storage is completed, a switching command is written in the control element switching unit 12. When the command is written, the control element switching unit 12 shifts to a standby state. Then, the first CPU 121 is reset and the operation is stopped. At this time, the power supply circuit 126 for the first CPU can cut off the power supply of the first CPU 121 at the time of reset, and sufficient power saving can be achieved.

  When the operation of the first CPU 121 is stopped, the second CPU 129 is released from the reset and reads the restart program instead. Since the second CPU 129 takes over the value of the internal register from the first CPU 121 by the restart program, the operation is resumed from the point where the second CPU 129 is stopped without initializing the peripheral circuit.

  When the second CPU 129 stops and the first CPU 121 operates, the second CPU 129 first stores the information in the internal register 128 in the RAM 24. Next, when the storage is completed, a switching command is written in the control element switching unit 12. When the command is written, the control element switching unit shifts to the normal state. Then, the second CPU 129 is reset and stops operating. At this time, the power supply circuit 126 for the first CPU resumes power supply. Instead, the first CPU 121 releases the reset and reads the restart program. Since the CPU 121 takes over the value of the internal register from the second CPU 129 by the restart program, the operation is resumed from the point where the second CPU 129 is stopped without damaging the print data received in the RAM 24.

The power applied to the control element in the second embodiment is compared. For example, assuming a use condition in which one hour of the day is in a normal state and the remaining 23 hours are in a standby state, the switching control is not performed and only the first CPU power saving mode is used. Power consumption = 20 W × 23 h + 100.0 W × 1 = 560 W, but if the operation in the second embodiment, power consumption per day = 0.1 W × 23 h + 100.0 W × 1 = 102 .3W is enough,
A power reduction effect of about 82% can be obtained.

  Further, when the first CPU 121 having a high clock frequency and a high processing capability is used as in the present embodiment, it can be seen that the power saving effect is increased by switching to a CPU having a low processing capability during standby. Further, by mounting an IP-like hard macro like the second CPU 129 in advance in the memory control unit, the number of components on the board can be reduced.

  In the second embodiment, the IP controller PPC405 CPU is mounted on the memory control unit 130. However, the number and size of LSIs and semiconductor chips can be reduced by using a CPU model with a small number of gates and an emulation technology using microcode. Is possible.

  In this embodiment, an example of an image forming apparatus including a printing apparatus has been described as an example of an electronic control apparatus. However, the present invention may be applied to other scanners, facsimile apparatuses, copiers, and combinations of these that are connected to a network. Further, the present invention may be applied to various devices such as other acoustic devices, mobile phones, home appliances, and peripheral devices that are controlled using a control device such as a CPU.

1 is a block diagram illustrating a connection example of a network including an image forming apparatus according to a first embodiment of the present invention. 1 is a block diagram illustrating a configuration example of an image forming apparatus according to a first embodiment of the present invention. FIG. 3 is a block diagram illustrating a configuration example of a control element switching unit of the image forming apparatus according to the first exemplary embodiment of the present invention. FIG. 3 is a state transition diagram of a state machine in the image forming apparatus according to the first embodiment of the present invention. 3 is a time chart showing a change of a state machine and a change of a signal in the image forming apparatus according to the first exemplary embodiment of the present invention. 6 is a time chart illustrating a change in signal when the state machine shifts from a standby state S3 to a normal state S4 in the image forming apparatus according to the first exemplary embodiment of the present invention. 4 is a flowchart illustrating a flow from turning on the power to printing, in the operation of the image forming apparatus according to the first exemplary embodiment of the present invention. 3 is a flowchart illustrating standby processing among operations of the image forming apparatus according to the first exemplary embodiment of the present invention. FIG. 3 is a block diagram illustrating a register group used in the image forming apparatus according to the first embodiment of the present invention. 4 is a flowchart for explaining CPU switching processing among operations of the image forming apparatus according to the first exemplary embodiment of the present invention. 5 is a flowchart for explaining a restart process in the operation of the image forming apparatus according to the first embodiment of the present invention. It is a block diagram which shows the structural example of the image forming apparatus of the 2nd Embodiment of this invention.

Explanation of symbols

1-3 User PC 4 Image forming apparatus 10 Network communication line 11 Network interface control unit 12 Control element switching unit 13 Interrupt signal line 14 CPU1_RESET signal line 15 CPU2_RESET signal line 16 First CPU
17 Second CPU
18 ROM_SWITCH signal line 19 Bus 20 Memory control unit 21 Image forming means 22 RAM bus 23 ROM bus 24 RAM
25 Reboot program area 26 ROM
27 Initial program areas 28 and 29 Internal register 40 Internal bus 41 Command analysis unit 42 ECO_MODE signal line 43 NOR_MODE signal line 44 State machine 48 Reset circuit 50 Internal register group 51 to 56 General-purpose register 57 Program counter 58 Link register 59 Memory conversion table register 60 Condition register 61 Master status register 62 Processor version register 120 Image forming apparatus 121 First CPU
122 Internal register 123 Power supply line 124 Reset signal line 125 Reset circuit 126 Power supply circuit 128 Internal register 129 Second CPU
130 Memory controller

Claims (12)

Peripheral circuits,
A first control element that operates with a predetermined power consumption and controls the peripheral circuit;
A second control element that operates with lower power consumption than the power consumption of the first control element and controls the peripheral circuit;
Switching in which the peripheral circuit is controlled by the first control element in the normal state, and the operation of the first control element is stopped and the peripheral circuit is controlled by the second control element in the standby state An electronic control device comprising: a control unit. When the element that controls the peripheral circuit switches between the first control element and the second control element,
The control element before switching stores processing information in the storage unit of the peripheral circuit,
The control element after switching reads the processing information stored in the storage unit of the peripheral circuit,
2. The electronic control device according to claim 1, wherein the control element after switching has a return control function for recovering to a state immediately before the control element before switching stops. 3. The electronic control device according to claim 2, wherein the processing information stored in the storage unit of the peripheral circuit is information of internal registers of the first and second control elements. After the element that controls the peripheral circuit is switched from the first control element to the second control element, the switching control unit stops the operation of the first control element and the first control element 2. The electronic control device according to claim 1, wherein the electronic control device has a power cutoff function for shutting off the supplied power. 5. The electronic control device according to claim 4, wherein a tristate buffer is disposed at an output portion of the first control element. After the element that controls the peripheral circuit is switched from the first control element to the second control element, the switching control unit stops the operation of the first control element and is supplied to the peripheral circuit. 2. The electronic control device according to claim 1, wherein the electronic control device has a power shut-off function for shutting off the power. The electronic control device according to claim 6, wherein the operation of shutting off the power supplied to the peripheral circuit is performed after a predetermined time has elapsed. The electronic control device according to claim 1, wherein the first control element and the second control element are compatible with a program to be calculated. The electronic control device according to claim 1, wherein the switching control unit switches the operation of the first control element and the second control element in accordance with a signal of a CPU bus. The electronic control apparatus according to claim 1, wherein the first control element and the second control element process print data.   The electronic control device according to claim 1, wherein the peripheral circuit includes an image forming unit that forms a predetermined image. After the element that controls the image forming unit is switched from the first control element to the second control element, the switching control unit stops the operation of the first control element and supplies the operation to the image forming unit. 12. The electronic control device according to claim 11, wherein the electronic control device has a power cut-off function for cutting off the power to be turned on.