JPH02304610A - Detecting device for turn-on and turn-off of power source of peripheral equipment - Google Patents

Abstract

PURPOSE:To detect the turn-on/turn-off state of a power source of a peripheral equipment and a connecting state of a cable by reading in an output signal of a monostable multivibrator, and discriminating a level of its output signal. CONSTITUTION:An output of a crystal oscillator 4 is brought to frequency division to a triggerable frequency by a monostable multivibrator 5, and a signal CLK is obtained. Subsequently, AND 6 of the CLK signal and an enable signal from a CPU 2 is taken and an SYSN signal is sent out to a peripheral equipment 11 side. When a power source of the equipment 11 is turned on, a monostable multivibrator 12 of the equipment 11 side is triggered, and an output pulse is outputted. The monostable multivibrator 12 is retriggered, and while a trigger pulse SYNC is inputted, its output 'STATE' remains a 'Low' level. The CPU 2 of a computer 1 side reads in this 'STATE' signal, and in the case of the 'Low' level, it can be confirmed that the power source of the equipment 11 is turned on, and a cable 16 is also connected normally. In the case of the 'High' level, it is decided that the power source of the equipment 11 is turned off, or the cable 16 is not connected yet.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for detecting power on/off of OA equipment in general, and in particular detects the power on/off state of a partner unit and the connection state of a cable. The present invention relates to a detection device.

[Prior art] - In conventional OA equipment, a detection device that detects the power on/off status of a partner unit, cable connection status, etc. has a status register in each peripheral device.
Some systems check the power on/off status of the other unit by mutually reading the status register of the other unit.

For example, as shown in FIG. 5, in a unit (A) 51 and a unit (B) 55 connected by a cable 59,
The tttrt of the unit (A) 51 is turned on to enable operation. Then, in the unit (A) 51, the CPU 52 sets a code such as "AA" in the status register 53. Unit (B) 5
5 reads the status register 53 of the unit (A) 51 via the transceiver 54, and the code is "AA".
If so, it can be confirmed that the unit (A) 51 is in an operable state. Similarly, unit (A) 5
1 indicates the power status of the unit (B) 55 by the CPU 56.
Status register 57. Via the transceiver 58,
You can check the status of both power supplies and the cable 59 as above.
This is to check the following.

[Problems to be Solved by the Invention] With a conventional OA device that detects the 1RI power on/off state and cable connection state of a partner unit using a status register, the state of the partner unit can be confirmed in detail. However, depending on the type of peripheral device, for example, there are many devices such as CRT displays that only need to be able to confirm whether the other party's power is on or off. A sensing device is required.

The conventional device that detects status using a status register has a complicated circuit and is expensive, making it unsuitable for detecting the power on/off state of peripheral equipment such as the above-mentioned CRT display.

The purpose of the present invention is to solve the problems of the prior art and to provide a simple and low-cost method that can detect the power on/off status of the counterpart unit and the cable connection status in conventional OA equipment. An object of the present invention is to provide a power on/off detection device for peripheral equipment.

[Means for Solving the Problems] In order to achieve the above object, the peripheral device power on/off detection device of the present invention provides: (1) one or more computers and their peripheral devices connected to each other by a cable; In the system, the computer has a circuit that sends a signal at a predetermined frequency to peripheral devices, and the peripheral device receives a signal at a predetermined frequency. A circuit that outputs the status of a bit is provided, and the computer determines the status of this one bit and detects the power on/off state of the peripheral device, which is the other unit, and the connection state of the cable. .

(2) A retriggerable monostable multivibrator is provided as a peripheral device, and the output pulse width of the monostable multivibrator is set to be greater than or equal to the period of the input trigger signal, so that the output of this monostable multivibrator is always set to 1. It is characterized in that it maintains the bit status and detects whether or not the input trigger signal is input.

[Operation] In the present invention, a computer that is turned on has the following functions:
First, the output of the built-in oscillator is divided to a frequency that can trigger the monostable multivibrator in the peripheral device.

Next, this frequency-divided clock pulse and the CPU
A signal is generated by ORing with the enable signal from to the corresponding peripheral device. The relevant peripheral device receives the signal resulting from this logical sum via the cable. At this time, when the peripheral device is powered on, the monostable multivibrator built into the peripheral device is triggered by the logical OR signal and outputs an output pulse. The period of this output pulse is set to be longer than the period of the trigger signal from the computer by a capacitor and a resistor connected to the monostable multivibrator. Therefore, the monostable multivibrator is retriggered by the trigger signal from the computer, and the output of the monostable multivibrator remains at a constant level while the signal from the computer is input. If this output is, for example, “Low”
”, the computer's CPU determines that the peripheral device is powered on normally.

In this way, the computer reads the output signal of this monostable multivibrator and determines the level of the output signal to turn on MltX of the peripheral device.
It becomes possible to detect the off state and the cable connection state.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a computer l and peripheral equipment 11 to which the present invention is applied.
FIG. 2 is a block circuit diagram showing connections.

The computer l includes a CPU 2 that performs overall control, and a memory 3. Crystal oscillator 4. Monostable multivibrator5. Logical product operation element 6. Flip-flop 7, inverter 8.
It is composed of an interface 9 and a bus IO. The peripheral equipment 11 includes a monostable multivibrator 12.
An interface 13, a capacitor 14, and a resistor 15 are provided. In addition, the computer l and peripheral equipment 11
are connected by a cable 16.

In FIG. 1, the computer l needs to confirm that the peripheral device 11 is powered on before exchanging data with the peripheral device 11. To achieve this purpose, the output of a crystal oscillator 4 used in the computer 1 is frequency-divided to a frequency that can be triggered by a monostable multivibrator 5 to obtain a signal CLK. The logical product of this CLK signal and the enable signal from the command from the CPU 2 to the flip-flop (F/F) 7 is taken, and the peripheral device 1
Sends the 5YNC signal to the 1 side. When the peripheral device 11 is powered on, the monostable multi-vibration brake 12 on the peripheral device ll side is triggered and outputs an output pulse (negative pulse). At this time, capacitor (C) +4 and resistor (R)
The output pulse width Tw determined by 15 is set longer than the period (T) of the 5YNC signal. Due to this,
The monostable multivibrator 12 is retriggered and its output "5TATE" remains at the "Low" level while the trigger pulse (SYNC) is input. Then, CPU2 on the computer l side uses this "5TATE"
"Read the signal through the inverter 8," Lo
w" level, it can be confirmed that fTlm of the peripheral device 11 is on and the cable 16 is also connected normally. Conversely, if the 5TATE" signal is at the "High" level, the peripheral device 11's fTlm is on. The power is off or the cable 16 is not connected.

In addition, when an abnormal state occurs on the peripheral equipment side, the monostable multivibrator 12 is activated by a clear signal (CLR).
), and by setting the 5TATE signal to "High", the abnormal state can be notified to the computer I side.

FIG. 2 is a timing chart showing the generation status of each signal in FIG. 1.

The signal "5YNC" obtained as a result of the AND of the signal "CLK" which is the frequency-divided output of the crystal oscillator 4 and the output signal "F/F-Q" of the flip-flop (F/F) 7 is T
and the period Tw of the output signal of the monostable multivibrator 12
The monostable multivibrator 12 continues to be triggered due to the difference between the two. Therefore, the output state '5TATE' of the monostable multivibrator 12 will maintain the 'Low' state. Note that the CLR signal is input to the monostable multivibrator 12 when the above occurs in the peripheral device 11, and the output state of the monostable multivibrator 12 is changed.
3 is a flowchart showing the operation of the CPU 2 on the computer l side of FIG. 1.

When the computer 1 is powered on, set the flip-flop 7 to II High ghI+ (step 30).
1). Wait until twice the period T of the signal "5YNC" has elapsed (step 302), and determine the state of the "STΔTE'" signal from the peripheral device 11 (step 30).
2).

If the "5TATE" signal is at the '84gh' level, it is determined that the power of the first peripheral device 11 is off, and the state of the "5TATE" signal is determined again (step 30).
3). If the "5TATE" signal is at the +L0W11 level, it is determined that the peripheral device 11 is powered on, and the detection operation is ended (step 305).

FIG. 4 shows a second embodiment of the present invention, and FIG. 5 (4) shows the computer 21 and the CRT display 28.
FIG.

The computer 21 has a CPU 22. Memory 23° oscillation'
It is composed of an IS 24, a CRT controller 25, and an inverter 26. CRT display 2
8 is a video circuit 29 and a monostable multivibrator 30
, and has a capacitor (C) 31 and a resistor (R) 32,
It is connected to the computer 21 by a cable 33.

FIG. 4(b) is a timing chart showing the state of the detection signal in the circuit of FIG. 4(a).

In the second embodiment shown in FIG. 4, the operation of detecting the power on/off state of the CRT display 28 by the computer 21 is almost the same as in the first embodiment shown in FIG. However, in the case of the second embodiment, the computer 21
The CRT controller 25 generates a constant frequency signal “H”.
3YNC'' is sent to the CRT display 28 through a cable 33.The period of this signal is sufficient to trigger the monostable multivibrator 30, so the clock frequency division required in the first embodiment is does not require.

Now, the monostable multivibrator 30 triggered by the signal 'H3YNC' whose period is T, has a period Tw.
Outputs the signal. This period Tw is the capacitor (
C) 31 and resistor (R) 32, the signal "l-1sY
Since it is set longer than the period T of Nc'', the monostable multivibrator 30 continues to be triggered, and its output "5TATE" is always "Low", indicating that the power of the CRT controller 25 on the computer 21 side is on. ,
Notify that it is operational.

[Effects of the Invention] According to the present invention, it is possible to realize a simple and low-cost power on/off detection circuit in a system in which a computer and peripheral devices are connected to each other by a cable.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing a computer, peripheral devices, and their connections according to a first embodiment of the present invention;
1 is a timing chart showing the states of each signal in the first embodiment shown in FIG. 1, FIG. 3 is a flowchart showing the operation of the CPU in the first embodiment shown in FIG. The second example of computer and CR
A block circuit diagram showing the T display and its connections, a timing chart showing the states of each signal, and FIG. 5 is a block diagram showing a power on/off detection circuit according to the prior art. l: Computer, 2: CPU, 3: Memory. 4: Crystal oscillator, 5: Monostable multivibrator. 6: AND operation element, 7: Flip-flop, 8: Inverter, 9: Interface, 10: Bus. 11 = peripheral equipment, 12: monostable multivibrator, 1
3: Interface, 14: Capacitor. 15: g resistance, 16: cable, 21: computer, 2
2: CPU, 23: Memory, 24: Oscillator. 25: CRT controller, 26: Inverter. 27: bus, 28: CRT display, 29: video circuit, 30: monostable multivibrator. 31: Capacitor (C), 32: Resistor (R), 33: Cable, 51: Unit (A), 52: CPU. 53: Status register, 54: Transceiver. 55: Unit (B), 56: CPU, 57: Status register, 58: Transceiver, 59: Cable. (,・ Figure 3 “−−−−−−−−−t−−−−−−−−＋＋−1st
4 Figure (Part 2) (b)

Claims (2)

[Claims] (1) One or more computers and their peripherals are
In a system connected to each other by cables, the computer includes means for sending a signal at a predetermined frequency to the peripheral device, and the peripheral device includes means for outputting a 1-bit status based on the signal at the frequency. A device for detecting power on/off of a peripheral device, wherein the computer determines the status of the one bit and detects the power on/off state of the peripheral device and the connection state of the cable. . (2) The above peripheral device is provided with a retriggerable monostable multivibrator, and the output pulse width of the monostable multivibrator is set to be greater than or equal to the period of the input trigger signal, so that the output of the monostable multivibrator is always set to 1. A peripheral device power-on/control device characterized by maintaining the bit status and detecting whether or not the above-mentioned input trigger signal is input.
Off detection device.