JPH0683642A - Interruption controller - Google Patents

Abstract

PURPOSE:To accept and process even the interruption requests that have the priority levels lower than those of the priority ordering interruption requests produced continuously by a defect. CONSTITUTION:An interruption end detecting logic 9 detects the end of the interruptions given from a microprocessor 14. An interruption mask data control logic 8 which receives an interruption end signal 108 generates the interruption mask data 110 based on the state of an interruption service register 6 set when the end of the interruptions is detected and an interruption request signal 105. Then the logic 8 writes the data 110 in an interruption mask register 7. The interruption processing jobs are carried on thereafter based on the data 110.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt controller in a microcomputer or the like, and more particularly to an interrupt controller for controlling the priority of a plurality of interrupt requests.

[0002]

2. Description of the Related Art Conventionally, an interrupt control device of this kind has been used together with a microprocessor to control an interrupt request from the outside to the microprocessor.

FIG. 8 is a block diagram of a conventional interrupt control device. As shown in FIG. 8, the conventional interrupt control device 1a includes an interrupt request register 4 for holding the state of an interrupt request signal 105 from an external device and an interrupt mask register 7 for holding interrupt request prohibition information. A priority determination logic 5 for determining the priority of the interrupt request 105, a control logic 3 for notifying the microprocessor 14 of the interrupt request, and an interrupt routine address generation logic 2 for generating an interrupt routine address 107. And an interrupt service register 6 for indicating the currently accepted interrupt request. In addition to these components, the interrupt control device 1a has a data bus buffer 10, a read / write control 11, and an internal data bus 12. The interrupt control device 1a is connected to the microprocessor 14 by a data bus 13, and has an interrupt (INT) signal 101 and an interrupt acknowledge (INTA) signal 102.
And the read signal 103 and the write signal 104 are transmitted and received. There are usually a plurality of interrupt request signals 105, each of which is connected to a device.

First, when an interrupt request is issued from each device, an interrupt request signal 105 is sent to the interrupt control device 1a and the interrupt request register 4 is set. When a plurality of interrupt requests are generated, the priority determination logic 5 refers to the contents of the interrupt mask register 7 and interrupt request signal 10
Determine the priority of 5. An interrupt request to the microprocessor 14 passes through the control logic 3 and an interrupt (IN
T) Signaled by signal 101.

Next, when the microprocessor 14 receives the interrupt signal (INT) 101 and determines that the interrupt may be accepted, the interrupt acknowledge (INTA) signal 1
02 is output to the control logic 3. Upon receiving the interrupt acknowledge (INTA) signal 102, the control logic 3 outputs the interrupt routine address generation signal 106 to the interrupt routine address generation logic 2. The interrupt routine address generation logic 2 uses the routine address 107 of the highest priority interrupt as the internal data bus 12.
The data is output to the data bus 13 via the data bus buffer 10. At this time, the corresponding interrupt request register 4 is cleared and the corresponding interrupt service register 6 is set.

On the other hand, the microprocessor 14 fetches the interrupt routine address 107 from the data bus 13,
Performs interrupt processing. When the interrupt processing in the microprocessor 14 is completed, the microprocessor 14 notifies the external device of the interrupt end data. This allows
The corresponding interrupt service register 6 is cleared. Also, the interrupt request signal 105 must be inactive by this time.

Further, the read / write control 11 receives a read (RD) signal 103 from the microprocessor 14.
A read or write control is performed by receiving a write (WR) signal 104 and a write or write (WR) signal 104;

FIG. 9 is a timing chart of the interrupt operation of the interrupt controller shown in FIG. As shown in FIG. 9, first, when the interrupt request signal 105 becomes active to notify that there is an interrupt request, the interrupt control device 1a causes the interrupt (I
NT) signal 101 is activated and output to the microprocessor 14. Next, the microprocessor 14 receives the interrupt (INT) signal 101 and then returns the interrupt acknowledge (INTA) signal 102. As the interrupt acknowledge signal 102, two pulses are transmitted.

On the other hand, the interrupt routine address 107 is output to the data bus 13 in response to the second pulse of the interrupt acknowledge (INTA) signal 102. Then, when the interrupt processing in the microprocessor 14 is completed, the microprocessor 14 notifies the external device of the interrupt end data. By this time interrupt request signal 10
5 must be inactive.

[0010]

The above-mentioned conventional interrupt control device inactivates an interrupt request when the processing for the interrupt request with a high priority is completed and before the completion of the interrupt is notified from the microprocessor. Need to Therefore, when a defect occurs in the interrupt request and the interrupt request remains active, it is determined that a new interrupt request has occurred and the interrupt processing is restarted. As a result, a low priority interrupt request cannot be accepted forever unless the contents of the interrupt mask register are changed by an instruction from the microprocessor.

An object of the present invention is to provide an interrupt control device which can accept an interrupt request of a low priority without changing the interrupt prohibition information even when such interrupt requests of a high priority occur successively. To do.

[0012]

SUMMARY OF THE INVENTION An interrupt control device of the present invention includes an interrupt prohibiting means for accepting a plurality of interrupt requests and determining a priority order, a means for holding prohibition information of the interrupt requests, and an interrupt for a microprocessor. A means for notifying a request, a means for generating an interrupt routine address and outputting it to the microprocessor, a means for detecting an interrupt end signal from the microprocessor, a state of the interrupt end detecting means and the interrupt request And means for doing so.

[0013]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram of an interrupt control device showing an embodiment of the present invention. As shown in FIG. 1, the interrupt control device 1 of the present embodiment has an interrupt request 10 from an external device.
5, the interrupt request register for holding the state of 5, the interrupt mask register 7 for holding the prohibition information of the interrupt request, the priority determination logic 5 for determining the priority order of the interrupt request, and the microprocessor for the interrupt request. 14
Control logic 3 for notifying the user, interrupt routine address generation logic 2 for generating an interrupt routine address, interrupt service register 6 for indicating the currently accepted interrupt request, and interrupt termination from microprocessor 14. Interrupt detection logic 9 for detecting the interrupt, and interrupt mask data for controlling the data to be written in the interrupt mask register 7 according to the state of the interrupt end detection logic 9 and the information from the interrupt request signal 105 and the interrupt service register 6. It has a control logic 8, a data bus buffer 10, a read / write control 11, and an internal data bus 12.
This interrupt control device 1 uses an interrupt (INT) signal 101
And an interrupt acknowledge (INTA) signal 102, a REIT signal 103 and a write signal 104 are exchanged with the microprocessor 14, and data is transferred by the data bus 13. There are usually a plurality of interrupt request signals 105, each of which is connected to a device.

First, when an interrupt request is issued from each device, the interrupt request signal 105 sets the interrupt request register 4 of the interrupt control device 1. At this time, when a plurality of interrupt requests are generated, the priority determination logic 5 refers to the contents of the interrupt mask register 7 and outputs the interrupt request signal 10
Determine the priority of 5. When the priority is determined by the priority determining logic 5, the control logic 3 is driven to make an interrupt request to the microprocessor 14. That is, the control logic 3 notifies by the interrupt (INT) signal 101.

Next, the microprocessor 14 receives the interrupt signal (INT) 101 and then outputs it to the control logic 3 of the interrupt control device 1. This microprocessor 1
When receiving the interrupt acknowledge (INTA) signal 102 from the control logic 4, the control logic 3 outputs the interrupt routine address generation signal 106 to the interrupt routine address generation logic 2. From the interrupt routine address generation circuit 2, the interrupt routine address 107 having the highest priority is stored in the internal data bus 12 and the data bus buffer 1.
It is output to the data bus 13 via 0. At this time,
The corresponding interrupt request register 4 is cleared and the corresponding interrupt service register 6 is set. On the other hand, the microprocessor 14 fetches the interrupt latency address 107 from the data bus 13 and executes interrupt processing.
Thereafter, when the interrupt processing in the microprocessor 14 is completed, the microprocessor 14 notifies the external device of the interrupt end data and clears the corresponding interrupt service register 6. As a result, the interrupt end detection logic 9 decodes the interrupt end data to generate the interrupt end signal 108, the interrupt request signal 105, and the interrupt service signal 10 from the interrupt service register 6.
9 and are input.

FIG. 2 is a block diagram of the interrupt mask data control logic shown in FIG. As shown in FIG. 2, the interrupt mask data control device 8 includes AND elements 24 to 26,
And the latches 21 to 23. Now, although one interrupt request signal 105 is accepted and the interrupt end data is notified thereafter, the interrupt request signal 1
Suppose 05 remains active. In such a case, the output signal of the AND element 24 of the corresponding interrupt request is activated. Therefore, interrupt end signal 1
Data is held in the corresponding latch 21 corresponding to 08, and the interrupt mask data 110 is output. Therefore,
The interrupt mask data 110 is the interrupt end signal 108.
Is written in the interrupt mask register 7 in correspondence with. Therefore, the interrupt request is disabled, and the interrupt request having a lower priority than the interrupt request can be accepted.

FIG. 3 is a block diagram of the interrupt end detection logic shown in FIG. As shown in FIG. 3, this interrupt end detection logic 9 includes EXNOR elements 27 to 29 and NAND.
And the element 30. These EXNOR elements 2
Data from the internal data bus 12 and interrupt end data are input to 7 to 29, and as a result, finally NAND
An interrupt end signal 108 is output from the element 30.

FIG. 4 is an operation timing chart of the interrupt mask data control logic shown in FIGS. As shown in FIG. 4, when the interrupt end data is sent to the data bus 13, the interrupt end detection logic 9 activates the interrupt end signal 108. Here, it is assumed that the interrupt request signal 105 input to the interrupt mask data control logic remains active when the interrupt end signal 108 can be sent. Therefore, the interrupt end signal 108
In response to the interrupt request signal 105 and the interrupt service signal 109, the interrupt mask data control logic 8 generates the interrupt mask data 110. If the interrupt mask register 7 is set by the interrupt mask data 110, the interrupt request is masked when the interrupt request signal 105 remains active, so that an interrupt request with a low priority can be accepted.

FIG. 5 is a block diagram of an interrupt mask data control logic in an interrupt control device for explaining another embodiment of the present invention. As shown in FIG. 5, the interrupt mask data control logic 8 in this embodiment has the rising detection circuits 31, 33 and 35 and the falling detection circuits 32 and 3.
4, 36, AND elements 24, 25, 26 for logically ANDing outputs of these detection circuits 31, 33, 35 and the interrupt request signal 105, and SR flip-flops 37, 3
8, 39 and latches 21, 22, 23 for temporarily storing the outputs of these flip-flops 37-39.

First, the operation is the same as that of the above-described embodiment until the interrupt request signal 105 is generated and the interrupt control device 1 outputs the interrupt routine address 107 to the microprocessor 14. At this time, since the corresponding interrupt request register 4 is cleared and the corresponding interrupt service register 6 is set, the flip-flop 37 of the interrupt mask data control logic 8 is set.
Then, the interrupt end data is sent to the microprocessor 14
When the corresponding interrupt request signal 105 remains active when notified from the flip-flop 3
Since 0 remains set, the interrupt end signal 10
The interrupt request signal 105 is prohibited in synchronization with 8.

Next, it is assumed that the corresponding interrupt request signal 105 becomes inactive before the interrupt end data is notified from the microprocessor 14. in this case,
Interrupt request signal 1 at the fall detection circuits 32, 34, 36
The falling edge of 05 is detected, and the flip-flops 37 to 39 are detected.
To reset. Then, the corresponding interrupt request signal 10
If 5 remains inactive, the contents of the interrupt mask register 7 are not changed and normal interrupt control is continued. Further, even when the corresponding interrupt request signal 105 becomes active again, the flip-flop 37 remains reset, so that the corresponding interrupt request is accepted.

As described above, in this embodiment, after one interrupt request becomes active and is accepted by the interrupt controller 1, this interrupt request is once inactivated before the notification of the completion of the interrupt from the microprocessor 14. Therefore, even if the interrupt request is generated again and becomes active, the control can be continued without prohibiting the interrupt request.

FIG. 6 is an operation timing chart when the interrupt request signal in the interrupt mask data control logic shown in FIG. 5 is never inactive. Figure 6
If the interrupt request signal 105 has never become inactive by the time the interrupt request signal 105 receives the interrupt end data from the microprocessor 14, the interrupt mask data 110 is output.

FIG. 7 is an operation timing chart when the interrupt request signal in the interrupt mask data control logic shown in FIG. 5 once becomes inactive. As shown in FIG. 7, the interrupt request signal 105 indicates that the microprocessor 14
When it becomes inactive once before receiving the interrupt end data from, and becomes active again, the interrupt mask data 110 is not output. Incidentally, 111 is the output of the flip-flop 37 in FIG.

[0025]

As described above, the interrupt control device of the present invention issues an interrupt request according to the interrupt end detection logic for detecting the interrupt end signal from the microprocessor and the state of the interrupt end detection logic and the interrupt request signal. By including the interrupt mask data control logic to prohibit, even when interrupt requests with high priority occur consecutively, low priority interrupt requests can be issued without changing the interrupt disable information by the instruction of the microprocessor. The effect is that it can be accepted.

[Brief description of drawings]

FIG. 1 is a block diagram of an interrupt control device showing an embodiment of the present invention.

FIG. 2 is a configuration diagram of an interrupt mask data control logic shown in FIG.

FIG. 3 is a configuration diagram of an interrupt end detection logic shown in FIG.

4 is an operation timing diagram of the interrupt mask data control logic shown in FIGS. 1 and 2. FIG.

FIG. 5 is a configuration diagram of an interrupt mask data control logic in an interrupt control device for explaining another embodiment of the present invention.

FIG. 6 is a timing diagram when the interrupt request signal in the interrupt mask data control logic shown in FIG. 5 is never inactive.

7 is an operation timing chart when the interrupt request signal in the interrupt mask data control logic shown in FIG. 5 once becomes inactive.

FIG. 8 is a block diagram of an interrupt control device showing a conventional example.

9 is an operation timing chart of the interrupt control device shown in FIG.

[Explanation of symbols]

 1 Interrupt Control Device 2 Interrupt Routine Address Generation Logic 3 Control Logic 4 Interrupt Request Register 5 Priority Determination Logic 6 Interrupt Service Register 7 Interrupt Mask Register 8 Interrupt Mask Data Control Logic 9 Interrupt End Detection Logic 12 Internal Data Bus 13 Data Bus 21-23 Latch 24-26 AND element 27-29 EXNOR element 30 NAND element 31, 33, 35 Rise detection circuit 32, 34, 36 Fall detection circuit 37-39 Flip-flop 101 Interrupt (INT) signal 105 Interrupt request signal 106 Interrupt routine address Generation signal 107 Interrupt routine address 108 Interrupt end signal 109 Interrupt service signal 110 Interrupt mask data

Claims (1)

[Claims] 1. A means for receiving a plurality of interrupt requests to determine a priority order, a means for holding prohibition information of the interrupt requests, a means for notifying the microprocessor of the interrupt requests, and an interrupt routine address for generating the interrupt requests. An interrupt control characterized by having means for outputting to the microprocessor, means for detecting an interrupt end signal from the microprocessor, and an interrupt prohibiting means for prohibiting the state of the interrupt end detecting means and the interrupt request. apparatus.