JP2009301116A - Interruption device and interruption system equipped with the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an interruption device for preventing the disappearance of interruption, and for specifying the type of interruption in a short time, and an interruption system equipped with this interruption device. <P>SOLUTION: Cards 15a to 15d as interruption devices are configured to be operated from a host CPU 11, and respectively provided with a register group (hardware interruption register group 24a and a software interruption register group 24b) for storing interruption information (flag) indicating the type of interruption to the host CPU 11 and an interruption issue unit 25 for, when a flag related with interruption whose interruption processing has been completed from the register group by the operation of the host CPU 11 is erased, confirming the presence/absence of the flag stored in the register group, and for, when there exists a flag stored in the register group, performing interruption based on the flag to the host CPU 11. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an interrupt device for interrupting a host device and an interrupt system including the device.

  2. Description of the Related Art Conventionally, computer systems generally use interrupts that temporarily suspend processing executed by a CPU (central processing unit) and preferentially execute other processing (interrupt processing). . By using such an interrupt, it is possible to cause the CPU to perform processing other than interrupt processing when no interrupt occurs, and to cause the CPU to prioritize interrupt processing only when an interrupt occurs. Effective use of resources can be achieved, and responsiveness can be improved. Even in a semiconductor test apparatus for testing a semiconductor device, interrupts are frequently used to notify the host CPU of error occurrence, measurement end, calculation end, data transfer end, and the like.

  FIG. 5 is a block diagram showing a main configuration of an interrupt system provided in a conventional semiconductor test apparatus. As shown in FIG. 5, the interrupt system 100 provided in the conventional semiconductor test apparatus includes a host CPU 101, a host bridge 102, a host CPU memory 103, bus bridges 104a and 104b, cards 105a to 105d, a host bus B100, an upper bus B101, And a lower-level bus B102, B103, which interrupts the host CPU 101 when an interrupt occurs in each of the cards 105a to 105d.

  The host CPU 101 comprehensively controls the operation of the semiconductor test apparatus. When there is an interrupt from the cards 105a to 105d, the host CPU 101 executes an interrupt process corresponding to the type. The host bridge 102 is connected to the host CPU 101 via the host bus B100, communicates with the host CPU 101, and controls acceptance of interrupts from each of the cards 105a to 105d. The host CPU memory 103 is mainly used by the host CPU 101 and can be accessed at high speed from the host CPU 101 via the host bus B 100 and the host bridge 102. The host CPU memory 103 can be accessed from the cards 105a to 105d via the lower buses B102 and B103, the bus bridges 104a and 104b, the upper bus B101, and the host bridge 102. The bus bridge 104a connects the upper bus B101 and the lower bus B102, and the bus bridge 104b connects the upper bus B101 and the lower bus B103.

  The cards 105a to 105d are cards provided with predetermined functions such as a pin electronics function, a power supply function, and a DC test function provided in a semiconductor test apparatus, for example. These cards 105 a to 105 d include a local CPU 111, an interrupt register 112, interrupt generation sources 113 and 114, an OR (logical sum) circuit 115, and an interrupt issuer 116. Here, for simplicity of explanation, the card 105a will be described.

  The local CPU 111 controls the operation of the card 105a and generates a software interrupt as necessary. The interrupt register 112 stores software interrupts generated by the local CPU 111. Interrupt generation sources 113 and 114 indicate generation sources of hardware interrupts generated in the card 105a. The OR circuit 115 calculates the logical sum of the contents of the interrupt register 112 and the interrupts generated by the interrupt generation sources 113 and 114. The interrupt issuer 116 issues an interrupt to the host CPU 101 according to the calculation result of the OR circuit 115.

  FIG. 6 is a timing chart showing an example of the operation of the interrupt system provided in the conventional semiconductor test apparatus. In the initial state, it is assumed that both the host CPU 101 and the host bridge 102 are in an idle state (standby state). First, as shown in FIG. 6, it is assumed that a hardware interrupt occurs at the interrupt generation source 113 of the card 105a at time t101. This hardware interrupt is input to the interrupt issuer 116 via the OR circuit 115, whereby an interrupt to the host CPU 101 is issued. The interrupt issued by the interrupt issuer 116 is input to the host bridge 102 via the lower bus B102, the bus bridge 104a, and the upper bus B101 in order.

  When an interrupt issued by the interrupt issuer 116 is input to the host bridge 102 in an idle state, the host bridge 102 enters an interrupt detection state and an interrupt request D101 is notified to the host CPU 101. When the host CPU 101 in the idle state receives the interrupt request D101, interrupt processing is started, and thereafter, a response notification R101 indicating that the interrupt request D101 has been received from the host CPU 101 to the host bridge 102 is made. When this response notification R101 is received, the host bridge 102 returns to the idle state.

  Next, assume that a hardware interrupt occurs at the interrupt source 114 at time t102. This hardware interrupt is also input to the interrupt issuer 116 via the OR circuit 115, whereby an interrupt to the host CPU 101 is issued. Here, since the host bridge 102 is in an idle state, when an interrupt issued by the interrupt issuer 116 is input, an interrupt detection state is entered and an interrupt request D102 is notified to the host CPU 101. However, when the interrupt request D102 is notified, the host CPU 101 is executing an interrupt process based on the hardware interrupt generated at time t101, and therefore holds the interrupt request D102 on hold.

  After that, when the interrupt processing based on the hardware interrupt generated at time t101 is completed at time t104, the host CPU 101 starts interrupt processing based on the interrupt request D102 and sends a response notification R102 to the host bridge 102. As a result, the host bridge 102 returns to the idle state. The operation when a hardware interrupt occurs in the card 105a has been described above, but the same operation is performed when a software interrupt occurs. The same operation is performed when an interrupt is issued from the other cards 105b to 105d.

For details of the conventional interrupt device or interrupt system, see, for example, the following Patent Documents 1 and 2.
JP-A-3-170886 JP-A-8-129057

  By the way, in the conventional interrupt system, as described above, the logical sum of hardware interrupt and software interrupt generated in one card is calculated, and the interrupt issuer 116 issues an interrupt to the host CPU 101 according to the calculation result. is doing. For this reason, there is a problem that the interrupt may be lost depending on the occurrence state of the hardware interrupt and the software interrupt in the card.

  For example, as shown in FIG. 6, a case is considered where a software interrupt generated in the local CPU 111 is written to the interrupt register 112 at time t103 and an interrupt to the host CPU 101 is issued by the interrupt issuer 116. In such a case, when the interrupt issued by the interrupt issuer 116 is input to the host bridge 102, the host bridge 102 is in the interrupt detection state. For this reason, the interrupt issued by the interrupt issuer 116 disappears.

  Further, as shown in FIG. 6, a case is considered where hardware interrupts are generated simultaneously at both the interrupt generation sources 113 and 114 at time t105. In such a case, hardware interrupts generated by the interrupt generation sources 113 and 114 are integrated into one through the OR circuit 115. As a result, one of the hardware interrupts generated at the interrupt generation sources 113 and 114 is lost.

  Further, in the conventional interrupt system, since the logical sum of a plurality of interrupts generated in the card is calculated, when the interrupt is notified to the host CPU 101, the type of the notified interrupt cannot be specified. Therefore, a register for storing information specifying the type of interrupt is provided in each of the cards 105a to 105d, and when the interrupt is notified, the contents of the register provided in the card from which the host CPU 101 has issued the interrupt can be read. By doing so, it is considered that the document of interruption can be specified. However, as shown in FIG. 5, the host bus B100, the upper bus B101, and the lower buses B102 and B103 are interposed between the host CPU 101 and the cards 105a to 105d, and it takes time to read the register. was there.

  The present invention has been made in view of the above circumstances, and provides an interrupt device that can prevent the disappearance of an interrupt and that can specify the type of interrupt in a short time, and an interrupt system including the interrupt device. For the purpose.

In order to solve the above-described problem, the interrupt device of the present invention is an interrupt device (15a to 15d) that interrupts the host device (11), and can be operated from the host device. When the interrupt information related to the interrupt for which the interrupt processing has been completed is erased from the storage unit by the operation of the higher-level device by storing the interrupt information indicating the type of interrupt to be performed (24a, 24b), An interrupt unit that checks the presence or absence of interrupt information stored in the storage unit, and performs an interrupt based on the interrupt information to the host device when there is interrupt information stored in the storage unit (25).
According to the present invention, when an interrupt occurs in the interrupt device, the interrupt information indicating the type is stored in the storage unit, the interrupt to the host device is performed, and the interrupt is completed when the interrupt processing is completed in the host device. Interrupt information related to processing is erased from the storage unit, and then the presence or absence of interrupt information stored in the storage unit is confirmed by the interrupt unit. When there is interrupt information stored in the storage unit, An interrupt based on the embedded information is made to the host device.
The interrupt device of the present invention further includes a completion information storage unit (24e) for storing completion information indicating that the interrupt processing performed by the host device is completed, and the interrupt unit stores the completion information storage When the completion information is stored in the storage unit, the presence / absence of interrupt information stored in the storage unit is confirmed.
In the interrupt device of the present invention, another interrupt may occur from when the interrupt unit interrupts the host device until the completion information is stored in the completion information storage unit. It is characterized in that no interruption is made to the host device.
The interrupt device according to the present invention includes a prohibition information storage unit that stores prohibition information indicating that an interrupt to the host device is prohibited based on interrupt information set by the host device and stored in the storage unit. 24c), and when the prohibition information is stored in the prohibition information storage unit, the interrupt unit interrupts the host device even if the interrupt information is stored in the storage unit It is characterized by not performing.
In order to solve the above-described problem, an interrupt system according to the present invention is an interrupt system according to any one of claims 1 to 4 in an interrupt system (1) that performs interrupt processing according to an interrupt that has occurred. 15a to 15d), the host device (11) as the host device that performs interrupt processing according to the interrupt performed by the interrupt device, and the contents stored in the storage unit are written and referred to by the host device And a secondary storage unit (13).
The interrupt system according to the present invention is characterized in that the interrupt device includes a write control unit (21) for writing the interrupt information in the sub storage unit and storing the interrupt information in the storage unit.

According to the present invention, when an interrupt occurs in the interrupt device, the interrupt information indicating the type is stored in the storage unit, the interrupt is made to the host device, the interrupt processing is completed in the host device, and the interrupt is completed. When the interrupt information related to the process is deleted from the storage unit, the presence or absence of the interrupt information stored in the storage unit is confirmed. If there is interrupt information stored in the storage unit, the interrupt is stored. Since the interrupt based on the information is performed on the host device, the loss of the interrupt can be prevented.
In addition, the interrupt information indicating the interrupt type described above is stored in the storage unit and stored in the secondary storage unit accessed by the host device (higher level device), so that the interrupt type can be specified in a short time. There is an effect that can be done.

  Hereinafter, an interrupt device and an interrupt system including the same according to an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a main configuration of an interrupt system according to an embodiment of the present invention. In the following, an interrupt system provided in a semiconductor test apparatus for testing a semiconductor device will be described as an example.

  As shown in FIG. 1, the interrupt system 1 according to the present embodiment includes a host CPU 11 (host device, host device), a host bridge 12, a host CPU memory 13 (sub storage unit), bus bridges 14a and 14b, and cards 15a to 15d. (Interrupt device) is a system that includes a host bus B0, an upper bus B1, and lower buses B2 and B3, and interrupts the host CPU 11 when an interrupt occurs in each of the cards 15a to 15d.

  The host CPU 11 comprehensively controls the operation of the semiconductor test apparatus. When there is an interrupt from the cards 15a to 15d, the host CPU 11 executes an interrupt process corresponding to the type. Although details will be described later, the host CPU 11 can access the register module 24 provided in the cards 15a to 15d, and can manipulate the stored contents of the registers. The host bridge 12 is connected to the host CPU 11 via the host bus B0, and communicates with the host CPU 11 to control the acceptance of interrupts from each of the cards 15a to 15d.

  The host CPU memory 13 is mainly used by the host CPU 11 and can be accessed at high speed from the host CPU 11 via the host bus B 0 and the host bridge 12. The host CPU memory 13 can also be accessed from the cards 15a to 15d via the lower buses B2 and B3, the bus bridges 14a and 14b, the upper bus B1 and the host bridge 12.

  Although details will be described later, in the host CPU memory 13, the contents stored in the hardware interrupt register group 24a and the software interrupt register group 24b of the register module 24 provided in the cards 15a to 15d may be written. . This is because the host CPU 11 specifies the type of interrupt in a short time. The bus bridge 14a connects the upper bus B1 and the lower bus B2, and the bus bridge 14b connects the upper bus B1 and the lower bus B3. As the upper bus B1 and the lower buses B2 and B3, for example, a peripheral component interconnect (PCI) bus or a PCI Express (registered trademark) bus can be used.

  The cards 15a to 15d are cards provided with predetermined functions such as a function of pin electronics, a function of a power supply, a function of performing a DC test, and the like provided in a semiconductor test apparatus. These cards 15a to 15d include a local CPU 21 (write control unit), interrupt generation sources 22 and 23, a register module 24, and an interrupt issuer 25 (interrupt unit). Here, in order to simplify the description, the card 15a will be described.

  The local CPU 21 controls the operation of the card 15a and generates a software interrupt as necessary. Here, examples of the software interrupt generated in the local CPU 21 include an interrupt for notifying the host CPU 11 that a predetermined calculation has been completed. The local CPU 21 controls to write the contents stored in the hardware interrupt register group 24 a and the software interrupt register group 24 b of the register module 24 in the host CPU memory 13 in response to a request from the host CPU 11.

  Interrupt generation sources 22 and 23 indicate generation sources of hardware interrupts generated in the card 15a. Here, as a hardware interrupt that occurs in the card 15a, for example, an interrupt for notifying the host CPU 11 of an error occurring in the card 15a, an interrupt for notifying the host CPU 11 of the end of measurement, or transfer of various data For example, an interrupt for notifying the host CPU 11 when the process is completed is given. Although only two interrupt sources 22 and 23 are shown in FIG. 1, there are as many interrupt sources as the number of hardware interrupts that can occur in the cards 15a to 15d.

  The register module 24 includes a hardware interrupt register group 24a (storage unit, first storage unit), a software interrupt register group 24b (storage unit, second storage unit), a mask register group 24c (prohibition information storage unit), and a clear register group. 24d and an interrupt processing completion register 24e (completion information storage unit), and stores information (interrupt information) indicating the type of interrupt. The contents of the register module 24 are updated by the local CPU 21, the interrupt generation sources 22 and 23, or the host CPU 11. FIG. 2 is a diagram illustrating a configuration example of the register module 24.

  The hardware interrupt register group 24a includes a register corresponding to each of the interrupt generation sources in the card 15a. When a hardware interrupt is generated from the interrupt generation source, the hardware interrupt register group 24a has a hardware corresponding to the register corresponding to the interrupt generation source. A flag (interrupt information) indicating that an interrupt has occurred is stored. For example, as shown in FIG. 1, when there are two interrupt generation sources 22 and 23 in the card 15a, the hardware interrupt register group 24a is provided with two registers r11 and r12 as shown in FIG. . By identifying the register in which the flag is stored with reference to the contents of the hardware interrupt register group 24a, the type of hardware interrupt generated in the card 15a can be identified.

  The software interrupt register group 24b includes registers corresponding to software interrupts that can occur in the card 15a (software interrupts that can be generated by the local CPU 21). A flag (interrupt information) indicating that a software interrupt has occurred is stored in the register corresponding to the interrupt. For example, when there are two software interrupts that can occur in the card 15a, two registers r21 and r22 are provided in the software interrupt register group 24b as shown in FIG. By identifying the register in which the flag is stored with reference to the contents of the software interrupt register group 24b, the type of software interrupt generated in the card 15a can be identified.

  The mask register group 24c includes a register corresponding to each of a register included in the hardware interrupt register group 24a and a register included in the software interrupt register group 24b, and a register included in the hardware interrupt register group 24a and the software interrupt register group 24b. Even if a flag is stored, a flag (prohibition information) indicating that the interrupt to the host CPU 11 is prohibited is stored. For example, as shown in FIG. 2, when the hardware interrupt register group 24a includes two registers r11 and r12 and the software interrupt register group 24b includes two registers r21 and r22, the mask register group 24c Includes registers r31, r32, r33, r34 corresponding to these registers r11, r12, r21, r22.

  The mask register group 24c is set by the host CPU 11 immediately after the power of the semiconductor test apparatus is turned on, for example, and is used to prevent unnecessary interruption while the host CPU 11 is performing initialization processing. The contents of a plurality of registers provided in the mask register group 24c can be set individually. Therefore, it is possible to use such that only an interrupt required by the host CPU 11 is issued to the host CPU 11.

  The clear register group 24d includes a register corresponding to each of the register included in the hardware interrupt register group 24a and the register included in the software interrupt register group 24b, and is stored in the hardware interrupt register group 24a and the software interrupt register group 24b. A flag indicating that the flag is to be erased (cleared) is stored. For example, as shown in FIG. 2, when the hardware interrupt register group 24a includes two registers r11 and r12 and the software interrupt register group 24b includes two registers r21 and r22, the mask register group 24c Includes registers r41, r42, r43, r44 corresponding to these registers r11, r12, r21, r22.

  The contents of the clear register group 24d are set by the host CPU 11. When a flag is stored in one or more of the registers r41 to r44 included in the clear register group 24d, the flag is stored in the register of the hardware interrupt register group 24a or the software interrupt register group 24b corresponding to the register in which the flag is stored. The flag is cleared. If the flag stored in the register of the hardware interrupt register group 24a or the software interrupt register group 24b is cleared, the flag of the corresponding register of the clear register group 24d is also cleared.

  The interrupt processing completion register 24e stores a flag (completion information) indicating that the interrupt processing is completed in the host CPU 11 when the host CPU 11 notifies the card 15a that the interrupt processing is completed. As shown in FIG. 2, only one interrupt processing completion register 24e is provided, and the interrupt completion register 24e clears the stored flag after notifying the interrupt issuer 25 of the cancellation of the interrupt generation. Note that the clear registers 24d and the interrupt completion register 24e may be cleared by self-reset or by the interrupt issuer 25.

  The interrupt issuer 25 issues an interrupt to the host CPU 11 with reference to the contents of the hardware interrupt register group 24a and the software interrupt register group 24b. However, even if another interrupt occurs in the card 15a after issuing an interrupt to the host CPU 11, a flag is stored in the interrupt processing completion register 24e (the interrupt processing based on the interrupt issued earlier by the host CPU 11 is completed). Do not issue an interrupt until

  Further, when a flag is stored in the interrupt processing completion register 24e, the interrupt issuer 25 refers to the contents of the hardware interrupt register group 24a and the software interrupt register group 24b to check the presence of the flag and stores the flag. If there is a flag, an interrupt to the host CPU 11 is issued based on the flag, and the flag stored in the interrupt processing completion register 24e is cleared.

  Next, the operation of the interrupt system 1 having the above configuration will be described. FIG. 3 is a timing chart showing a first operation example of the interrupt system according to the embodiment of the present invention. Hereinafter, in order to simplify the description, it is assumed that no flags are stored in all the registers r31 to r34 included in the mask register group 24c. In the initial state, it is assumed that both the host CPU 11 and the host bridge 12 are in an idle state (standby state).

  First, as shown in FIG. 3, it is assumed that a hardware interrupt occurs at the interrupt generation source 22 of the card 15a at time t1. When this hardware interrupt occurs, a flag is stored in a register corresponding to the interrupt generation source 22 (register r11 included in the hardware interrupt register group 24a). The interrupt issuer 25 constantly monitors the hardware interrupt register group 24a and the software interrupt register group 24b, and when a flag is stored in any of the registers r11, r12, r21, r22 included therein, the host CPU 11 Issue an interrupt for. In the example shown in FIG. 3, since a flag is stored in the register r11, an interrupt to the host CPU 11 is issued. The interrupt issued by the interrupt issuer 25 is input to the host bridge 12 via the lower bus B2, the bus bridge 14a, and the upper bus B1 in this order.

  When the interrupt issued by the interrupt issuer 25 is input to the host bridge 12 in the idle state, the host bridge 12 enters the interrupt detection state and the host CPU 11 is notified of the interrupt request D1. When the host CPU 11 in the idle state receives the interrupt request D1, interrupt processing is started, and thereafter, a response notification R1 indicating that the interrupt request D1 has been received from the host CPU 11 to the host bridge 12 is made. Upon receiving this response notification R1, the host bridge 12 returns to the idle state.

  Here, it is assumed that a hardware interrupt is generated at the interrupt generation source 23 of the card 15a at time t2 after an interrupt to the host CPU 11 based on the hardware interrupt generated at time t1 is issued by the interrupt issuer 25. Then, the flag is stored in the register corresponding to the interrupt generation source 23 (register r12 included in the hardware interrupt register group 24a), but since the flag is not stored in the interrupt processing completion register 24e, the interrupt issuer 25 sends the host. An interrupt to the CPU 11 is not issued.

  When the host CPU 11 sends the response notification R1 to the host bridge 12, the stored contents of the hardware interrupt register group 24a and the software interrupt register group 24b provided in the card 15a to which the interrupt has been issued are read, and the interrupt The type is determined (time t3). In the example shown in FIG. 3, flags are stored in the registers r11 and r12 provided in the hardware interrupt register group 24a, and no flags are stored in the registers r21 and r22 provided in the software interrupt register group 24b. Therefore, the host CPU 11 can determine that the hardware interrupt has occurred at the interrupt generation sources 22 and 23 of the card 15a. As a result, the host CPU 11 performs an interrupt process according to the hardware interrupt generated by the interrupt generation sources 22 and 23 of the card 15a.

  Here, it is assumed that a software interrupt occurs in the local CPU 21 provided in the card 15a after the reading process by the host CPU 11 at the time t3 is completed. As a result, as shown in FIG. 3, it is assumed that flags are stored in the registers r21 and r22 provided in the software interrupt register group 24b. Even if a flag is stored in the registers r21 and r22, no interrupt is issued from the interrupt issuer 25 to the host CPU 11 because no flag is stored in the interrupt processing completion register 24e.

  When all the interrupt processing based on the interrupt determined at time t3 is completed, the host CPU 11 accesses the hardware interrupt register group 24a and the software interrupt register group 24b provided in the card 15a and relates to the interrupt that has finished the interrupt processing. The flag is cleared (time t4). In the example shown in FIG. 3, the flags stored in the registers r11 and r12 provided in the hardware interrupt register group 24a are cleared. Here, referring to FIG. 3, flags are stored in the registers r21 and r22 provided in the software interrupt register group 24b, but these are not cleared because they are not determined at time t3.

  When the above process is completed, a completion notification F1 indicating that the interrupt process has been completed is sent to the card 15a that issued the interrupt from the host CPU 11. When the completion notification F1 is made, a flag is stored in the interrupt processing completion register 24e provided in the card 15a. Then, the interrupt issuer 25 refers to the contents of the hardware interrupt register group 24a and the software interrupt register group 24b and confirms the presence or absence of the flag (time t5). In the example shown in FIG. 3, no flags are stored in the registers r11 and r12 provided in the hardware interrupt register group 24a, but flags are stored in the registers r21 and r22 provided in the software interrupt register group 24b. Yes. Thereby, an interrupt to the host CPU 11 is issued by the interrupt issuer 25.

  The interrupt issued by the interrupt issuer 25 is input to the host bridge 12 in the idle state via the lower bus B2, the bus bridge 14a, and the upper bus B1 in this order. Then, the host bridge 12 enters an interrupt detection state and an interrupt request D2 is notified to the host CPU 11. Here, since the host CPU 11 is executing the interrupt process at the time when the interrupt request D2 is notified, the interrupt request D2 is suspended. After that, when the interrupt processing is completed at time t6, the host CPU 11 starts interrupt processing based on the interrupt request D2 and sends a response notification R2 to the host bridge 12, thereby returning the host bridge 12 to the idle state. .

  When the host CPU 11 sends a response notification R2 to the host bridge 12, the stored contents of the hardware interrupt register group 24a and the software interrupt register group 24b provided in the card 15a to which the interrupt is issued are read, and the type of interrupt is determined. Determine (time t7). In the example shown in FIG. 3, no flags are stored in the registers r11 and r12 provided in the hardware interrupt register group 24a, and no flags are stored in the registers r21 and r22 provided in the software interrupt register group 24b. Therefore, the host CPU 11 can determine that the software interrupt has occurred in the local CPU 21 of the card 15a. As a result, the host CPU 11 performs an interrupt process according to the software interrupt.

  Next, when all the interrupt processing based on the interrupt determined at time t7 is completed, the host CPU 11 accesses the hardware interrupt register group 24a and the software interrupt register group 24b provided in the card 15a to complete the interrupt processing. Is cleared (time t8). In the example shown in FIG. 3, the flags stored in the registers r21 and r22 provided in the software interrupt register group 24b are cleared. When the above processing is completed, a completion notification F2 indicating that the interrupt processing is completed is sent to the card 15a that issued the interrupt from the host CPU 11, and a flag is set in the interrupt processing completion register 24e provided in the card 15a. Remembered.

  Then, the interrupt issuer 25 refers to the contents of the hardware interrupt register group 24a and the software interrupt register group 24b and confirms the presence or absence of the flag (time t9). In the example shown in FIG. 3, no flags are stored in any of the registers r11 and r12 provided in the hardware interrupt register group 24a and the registers r21 and r22 provided in the software interrupt register group 24b. No interruption to the host CPU 11 by 25 is issued.

  Next, another operation of the interrupt system 1 having the above configuration will be described. FIG. 4 is a timing chart showing a second operation example of the interrupt system according to the embodiment of the present invention. Here again, it is assumed that no flags are stored in all the registers r31 to r34 included in the mask register group 24c. In the initial state, it is assumed that both the host CPU 11 and the host bridge 12 are in an idle state (standby state).

  First, as shown in FIG. 4, it is assumed that hardware interrupts are generated simultaneously at both the interrupt generation sources 22 and 23 of the card 15a at time t11. When these hardware interrupts occur, flags are stored in registers corresponding to the interrupt generation sources 22 and 23 (registers r11 and r12 provided in the hardware interrupt register group 24a), respectively. Then, an interrupt to the host CPU 11 is issued by the interrupt issuer 25.

  The interrupt issued by the interrupt issuer 25 is input to the host bridge 12 via the lower bus B2, the bus bridge 14a, and the upper bus B1 in this order, whereby the host bridge 12 enters an interrupt detection state and is sent to the host CPU 11. An interrupt request D3 is notified. When the host CPU 11 in the idle state receives the interrupt request D3, interrupt processing is started, and thereafter, a response notification R3 indicating that the interrupt request D3 has been received from the host CPU 11 to the host bridge 12 is made. When this response notification R3 is received, the host bridge 12 returns to the idle state.

  When the host CPU 11 sends the response notification R3 to the host bridge 12, the stored contents of the hardware interrupt register group 24a and the software interrupt register group 24b provided in the card 15a to which the interrupt has been issued are read, and the interrupt The type is determined (time t12). In the example shown in FIG. 4, flags are stored in the registers r11 and r12 provided in the hardware interrupt register group 24a, and no flags are stored in the registers r21 and r22 provided in the software interrupt register group 24b. Therefore, the host CPU 11 can determine that the hardware interrupt has occurred at the interrupt generation sources 22 and 23 of the card 15a. As a result, the host CPU 11 performs an interrupt process according to the hardware interrupt generated by the interrupt generation sources 22 and 23 of the card 15a.

  When all the interrupt processing based on the interrupt determined at time t3 is completed, the host CPU 11 accesses the hardware interrupt register group 24a and the software interrupt register group 24b provided in the card 15a and relates to the interrupt that has finished the interrupt processing. The flag is cleared (time t13). In the example shown in FIG. 4, the flags stored in the registers r11 and r12 provided in the hardware interrupt register group 24a are cleared.

  When the above processing is completed, a completion notification F3 indicating that the interrupt processing has been completed is sent to the card 15a that issued the interrupt from the host CPU 11, and a flag is stored in the interrupt processing completion register 24e provided in the card 15a. Is done. Then, the interrupt issuer 25 refers to the contents of the hardware interrupt register group 24a and the software interrupt register group 24b and confirms the presence or absence of the flag (time t14). In the example shown in FIG. 4, no flags are stored in any of the registers r11 and r12 provided in the hardware interrupt register group 24a and the registers r21 and r22 provided in the software interrupt register group 24b. No interruption to the host CPU 11 by 25 is issued.

  As described above, in this embodiment, each of the cards 15a to 15d is provided with a register group (a hardware interrupt register group 24a and a software interrupt register group 24b) having a register corresponding to each of interrupts that can be generated internally. When an interrupt occurs, a flag is stored in the corresponding register. When the flag related to the interrupt for which the interrupt processing has been completed in the host CPU 11 is cleared from the register group, the interrupt issuer 25 checks the presence or absence of the flag stored in the register group, and the flag is stored. Is interrupted to the host CPU 11. For this reason, even when an interrupt to the host CPU 11 is issued when the host bridge 12 is in the interrupt detection state, or when a plurality of interrupts are simultaneously generated inside the cards 15a to 15d. , Can prevent the loss of interrupts.

  The interrupt device according to the embodiment of the present invention and the interrupt system including the interrupt device have been described above. However, the present invention is not limited to the above-described embodiment, and can be freely changed within the scope of the present invention. For example, in the above embodiment, when the host CPU 11 specifies the type of interrupt, the flag stored in the hardware interrupt register group 24a and the software interrupt register group 24b is read (for example, at time t3 in FIG. 3). t8).

  However, it is desirable to write the contents stored in the hardware interrupt register group 24 a and the contents stored in the software interrupt register group 24 b to the host CPU memory 13 and read the flag from the host CPU memory 13. As a result, the time required for the host CPU 11 to read the flag can be shortened, so that the time required to specify the type of interrupt can be shortened.

  The writing to the host CPU memory 13 is performed according to the following procedure. That is, when an interrupt occurs in the card, the local CPU 21 first writes a flag to the host CPU memory 13, and then the local CPU 21 writes to the hardware interrupt register group 24a or the software interrupt register group 24b.

  Here, when writing to the hardware interrupt register group 24 a or the software interrupt register group 24 b is performed, an interrupt to the host CPU 11 is issued by the interrupt issuer 25. For this reason, if writing to the hardware interrupt register group 24a or the software interrupt register group 24b is performed before writing to the host CPU memory 13, a flag required when the host CPU 11 accesses the host CPU memory 13 is displayed as a host. There may be a situation in which it is not stored in the CPU memory 13. In order to prevent such a situation, it is necessary to write a flag to the host CPU memory 13 before writing to the hardware interrupt register group 24a or the software interrupt register group 24b.

  In the above embodiment, for the sake of simplicity of explanation, the hardware interrupt register group 24a includes two registers r11 and r12, and the software interrupt register group 24b includes two registers r21 and r22. As described above, the number of registers can be appropriately determined according to the number of interrupts that can occur in the card. Further, the present invention can be applied to any type of interrupt of an edge trigger type interrupt and a level trigger type interrupt.

  Furthermore, in the above-described embodiment, an example has been described in which a register corresponding to each of the interrupts that can occur in the cards 15a to 15d is provided and a flag is stored in the register corresponding to the interrupt when an interrupt occurs. However, a plurality of registers may be collectively used as a multi-bit register, and the type of interrupt may be expressed by a code. For example, if the registers r21 and r22 shown in FIG. 2 are combined into a 2-bit register, four codes “00”, “01”, “10”, and “11” can be used. 4 types of interrupts can be stored. However, such a usage method uses another interrupt (especially, software interrupt register 24b (r21, r22) in the same card while the host CPU 11 is executing an interrupt process related to an interrupt generated in a certain card. The condition is that no interrupt occurred.

It is a block diagram which shows the principal part structure of the interruption system by one Embodiment of this invention. 3 is a diagram illustrating a configuration example of a register module 24. FIG. It is a timing chart which shows the 1st operation example of the interruption system by one Embodiment of this invention. It is a timing chart which shows the 2nd operation example of the interruption system by one Embodiment of this invention. It is a block diagram which shows the principal part structure of the interruption system with which the conventional semiconductor test apparatus is provided. It is a timing chart which shows an example of operation | movement of the interruption system with which the conventional semiconductor test apparatus is provided.

Explanation of symbols

1 Interrupt system 11 Host CPU
13 Host CPU memory 15a to 15d Card 21 Local CPU
24a Hardware interrupt register group 24b Software interrupt register group 24c Mask register group 24e Interrupt processing completion register 25 Interrupt issuer

Claims (6)

In the interrupt device that interrupts the host device,
A storage unit that is operable from the host device and stores interrupt information indicating a type of interrupt to be performed on the host device;
When interrupt information related to an interrupt for which interrupt processing has been completed is erased from the storage unit by an operation of the host device, the presence or absence of interrupt information stored in the storage unit is confirmed and stored in the storage unit An interrupt device, comprising: an interrupt unit that performs an interrupt based on the interrupt information to the host device when there is interrupt information that has been interrupted. A completion information storage unit for storing completion information indicating that the interrupt processing performed by the host device is completed;
The interrupt device according to claim 1, wherein when the completion information is stored in the completion information storage unit, the interrupt unit checks whether there is interrupt information stored in the storage unit. .   The interrupt unit does not interrupt the host device even if another interrupt is generated until the completion information is stored in the completion information storage unit after interrupting the host device. The interruption device according to claim 2. A prohibition information storage unit configured to store prohibition information indicating that the interrupt to the host device based on the interrupt information set by the host device and stored in the storage unit is prohibited;
When the prohibition information is stored in the prohibition information storage unit, the interrupt unit does not interrupt the host device even if the interrupt information is stored in the storage unit. The interrupt device according to any one of claims 1 to 3. In the interrupt system that performs interrupt processing according to the interrupt that occurred,
An interrupt device according to any one of claims 1 to 4,
A host device as the host device that performs interrupt processing according to an interrupt performed by the interrupt device;
An interrupt system comprising: a sub-storage unit to which content stored in the storage unit is written and referred to by the host device.   6. The interrupt system according to claim 5, wherein the interrupt device includes a write control unit that writes the interrupt information in the sub storage unit and stores the interrupt information in the storage unit.

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