JPH0728752A - Interface register - Google Patents

Abstract

PURPOSE:To provide an interface register which can produce an interruption signal even when the interruption cancel of a subsystem overlaps the interruption request of a main system. CONSTITUTION:An interface register 1 is connected to a main system via an address/data bus 2 and a control signal line 4 and also connected to a subsystem via an address/data bus 3, a control signal line 5 and an interruption signal line 6. Then both buses 2 and 3 of both systems are connected to the AND circuits 11 and 12 via the selecting circuits 8 and 9 respectively. At the same time, both lines 4 and 5 of both systems are also connected to the circuits 11 and 12 respectively. Then both circuits 11 and 12 are connected to the input of a double clock register 13, and the output fo the register 13 is connected to the line 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface register used for communication between two systems.

[0002]

2. Description of the Related Art In computers, a subsystem is often incorporated into a main system for the purpose of expanding the functions of the main system or reducing the load on the main system. As a subsystem in this case,
A communication board etc. are mentioned. When the main system requests processing from the subsystem, some communication means between both systems is required. When the subsystem is composed of a microcomputer system using a microprocessor, an interrupt request to the microprocessor is
It is often used as a means of communication between the main system and subsystems. In order to make an interrupt request to the microprocessor, an interrupt signal must be output to the interrupt input of the microprocessor. Upon receiving the interrupt signal, the processor interrupts the current processing, switches to a predetermined processing, and performs the processing requested by the main system.

Interface registers are used to output interrupt signals. FIG. 5 shows the interface register 1. Interface register 1
Is connected to the main system through the address / data bus 2 and the control signal line 4, and the address / data bus 3,
It is connected to the subsystem via the control signal line 5 and the interrupt signal line 6. The interface register 1 allows the main system to generate an interrupt signal by writing specific data to a specific address. Further, the interface register 1 allows the subsystem that has completed the processing requested by the main system to cancel the interrupt signal by writing specific data to a specific address.

A configuration example of the conventional interface register 1 using the D flip-flop 7 will be described with reference to FIG. For the D flip-flop 7, a 74LS74A or the like is used as a general-purpose IC.

The data (D) input of the D flip-flop 7 is connected to the power supply (+ 5V) for the purpose of raising the output at the rising edge of the clock (CLK) input. The address / data bus 2 is connected to the input of the selection circuit 8 for the purpose of raising the clock (CLK) input of the D flip-flop 7 when the main system writes specific data to a specific address. ,
The output of the selection circuit 8 is connected to the input of the AND circuit 11, the control signal line 4 is connected to the other input of the AND circuit 11, and the output of the AND circuit 11 is the clock (CLK) of the D flip-flop 7. Connected to input. Similarly, when the subsystem writes specific data to a specific address, an address is input to the selection circuit 9 for the purpose of setting the reset (R) input of the D flip-flop 7 to “L”. / Data bus 3 is connected, the output of the selection circuit 9 is connected to the input of the NAND circuit 10, the control signal 5 is connected to the other input of the NAND circuit 10, and the output of the NAND circuit 10 is the D flip-flop. It is connected to the reset (R) input. Further, the output (Q) of the D flip-flop 7 is connected to the interrupt signal line 6.

The operation of the interface register 1 will be described with reference to the time chart of FIG. At point A,
The main system writes specific data at a specific address, and the clock of the D flip-flop 7 (CL
K) input rises, the output (Q) of the D flip-flop 7 becomes “H”, an interrupt signal is output, and an interrupt occurs. After that, at the point B, the subsystem writes specific data at a specific address, the reset (R) input of the D flip-flop 7 becomes “L”, and the output (Q) of the D flip-flop 7 becomes “L”. The output of the interrupt signal is stopped and the interrupt is released.

[0007]

In the conventional interface register, when the interrupt release on the subsystem side and the interrupt request on the main system side overlap with each other, the reset input (R) of the D flip-flop 7, as shown in FIG. Is "L", the clock input (CLK) rises, and the interrupt signal cannot be generated. Therefore, the main system cannot request the subsystem to perform any operation,
It becomes an instability factor of the whole system.

An object of the present invention is to solve the conventional problems and provide an interface register capable of generating an interrupt signal even when an interrupt release on the subsystem side and an interrupt request on the main system side overlap. is there.

[0009]

The first gist of the present invention is as follows.
In the interface register connected to the main system via the address / data bus and the control signal line and connected to the subsystem via another address / data bus, the control signal line and the interrupt signal line, the main system and the subsystem Address / data bus of each is connected to each AND circuit through each selection circuit,
Further, the control signal lines of the main system and the subsystem are connected to the respective AND circuits, both AND circuits are connected to the inputs of the two clock registers, and the outputs of the two clock registers are connected to the interrupt signal line.

The second gist of the present invention is that the two clock registers are composed of an oscillator circuit and an edge detection circuit, and a set signal is output to the edge detection circuit by catching the rising of the output of the oscillator. The purpose is to catch the fall of the output of the oscillator and output a reset signal to the edge detection circuit.

[0011]

The interrupt output of the interface register is used as the output of the edge detection circuit, and the set / reset operation of the edge detection circuit is used as the edge operation of the corresponding control signal.
By setting the input timing of the control signal to the edge operation of the output signal of the oscillator and the edge operation of the inverted output,
Prevents the interrupt request from the main system and the interrupt release from the subsystem from overlapping.

[0012]

EXAMPLES Examples of the present invention will be described below.

A configuration example of the interface register 1 of the present invention will be described with reference to FIG.

The address / data bus 2 is connected to the input of the selection circuit 8 for the purpose of raising the clock input (CLK1) of the 2-clock register 13 when the main system writes specific data to a specific address. The output of the selection circuit 8 is connected to the input of the AND circuit 11, the control signal line 4 is connected to the other input of the AND circuit 11, and the output of the AND circuit 11 is 2
It is connected to the clock input (CLK1) of the clock register 13. Similarly, for the purpose of raising the clock input (CLK2) of the 2-clock register 13 when the subsystem writes specific data to a specific address, the address / data bus 3 is connected to the input of the selection circuit 9. Are connected, and the output of the selection circuit 9 is ANDed.
The AND circuit 12 connected to the input of the circuit 12
The control signal line 5 is connected to the other input of, and the output of the AND circuit 12 is connected to the clock input (CLK2) of the two-clock register 13. Further, the output of the 2-clock register 13 is connected to the interrupt signal line 6.

The interface of the present invention will be described with reference to FIG.
A configuration example of the two-clock register that constitutes the register will be described. The edge detection circuit 2 in the embodiment of FIG.
2 is set operation input CLK1, reset operation input C
LK2, and operates at the rising edge of each input.

An oscillator 14 is provided for the purpose of preventing CLK1 and CLK2 from rising at the same time.
It is output to the flip-flops 15 and 16. The D flip-flop 15 receives the output from the AND circuit 11 by the rising edge of the output of the oscillator 14 by using the output (CLK) of the oscillator 14 as a clock input, and the output of the D flip-flop 15 is
7 clock inputs (CLK1). Similarly, the D flip-flop 16 receives the output from the AND circuit 12 by the falling edge of the output of the oscillator 14 by using the inverted output of the oscillator 14 as a clock input, and the output of the D flip-flop 16 is D It is connected to the clock input (CLK2) of the flip-flop 18. D flip-flops 17 and 18 are provided for the purpose of detecting the overlap of CLK1 and CLK2, and output to AND circuits 19 and 20, respectively. AN
The D circuit 19 removes, from the inverted output of the D flip-flop 18, the portion of the waveform of CLK1 overlapping with CLK2, and outputs the result to the set input of the RS flip-flop 21. On the other hand, the AND circuit 20 includes the D flip-flop 17
The inverted output of CLK2 removes the portion of CLK2 overlapping with CLK1 and outputs it to the reset input of the RS flip-flop 21.

The operation of the edge detection circuit 22 in the interface register of the present invention will be described with reference to the timing chart of FIG.

At point A, the oscillator 14 (CLK) falls, CLK2 rises by catching the falling edge of CLK, then CLK rises at point B, and CLK1 rises by catching the rising edge of CLK. Further, consider a case where CLK2 falls at point C and CLK1 falls at point D, and CLK1 and CLK2 overlap. Since the D flip-flop 18 is reset by CLK1 up to the point B, the inverted output remains "H" even if CLK2 connected to the clock input rises at the point A. On the other hand, since the D flip-flop 17 is not reset by CLK2 between the points A and C, the inverted output becomes "L" due to the rising of CLK1 connected to the clock input at the point B. After that, when passing point C, it is reset by CLK2, so the inverted output of the D flip-flop 17 becomes "H". An AND circuit 19 outputs the logical product of the inverted output of the D flip-flop 18 and CLK1 to the set input of the RS flip-flop 21. Since the inverted output of the D flip-flop 18 is "H", CLK1 remains R-
It is output to the set input of the S flip-flop 21.

On the other hand, to the reset input of the RS flip-flop 21, the AND circuit 20 outputs the logical product of the inverted output of the D flip-flop 17 and CLK2.
Since the inverted output of the D flip-flop 17 is “L” from the point B to the point C, the waveform of CLK2 in which the point B to the point C is “L” is reset by the RS flip-flop 21. It is output to the input.

Therefore, the interrupt signal output from the RS flip-flop 21 falls at a point A where CLK2 rises when CLK falls, and rises at a point B where CLK1 rises when CLK rises.

[0021]

The set signal is output to the edge detection circuit by capturing the rising edge of the output of the oscillator, and the reset signal is output to the edge detection circuit by capturing the falling edge of the output of the oscillator. Interrupt requests are not canceled at the same time. Therefore, even if the host system makes an interrupt request, the interrupt signal is less likely to be generated, and the main system can reliably request the subsystem for processing.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an interface register of the present invention.

FIG. 2 shows a clock of the interface register of the present invention.
It is one block diagram which showed the detail of the register.

FIG. 3 is a diagram showing an operation of an interface register of the present invention.

FIG. 4 is a diagram showing an inconvenient operation of a conventional interface register.

FIG. 5 is a configuration diagram showing an example of a conventional interface register.

FIG. 6 is a diagram showing a normal operation of a conventional interface register.

[Explanation of symbols]

 1 interface register 2 address / data bus 3 address / data bus 4 control signal line 5 control signal line 6 interrupt signal line 7 D flip-flop 8 selection circuit 9 selection circuit 10 NAND circuit 11 AND circuit 12 AND circuit 13 2 clock register 14 Oscillator 15, 16, 17, 18 D flip-flop 19, 20 AND circuit 21 RS flip-flop 22 Edge detection circuit

Claims (2)

[Claims] 1. An interface register connected to a main system via an address / data bus and a control signal line, and connected to a subsystem via another address / data bus, a control signal line and an interrupt signal line,
The address / data buses of the main system and the subsystem are connected to the respective AND circuits through the respective selection circuits, and the control signal lines of the main system and the subsystem are connected to the respective AND circuits, and both AND circuits are 2 clocks. An interface register in which the input of the register is connected and the output of the two clock register is connected to an interrupt signal line. 2. The two-clock register comprises an oscillator circuit and an edge detection circuit, which captures the rising edge of the output of the oscillator and outputs a set signal to the edge detection circuit.
2. The interface register according to claim 1, wherein a falling edge of the output of the oscillator is detected and a reset signal is output to the edge detection circuit.