JPH1153049A - Computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption of a computer by enabling control over the stop and restart of a bus clock without mounting any special function on a peripheral device on a bus. SOLUTION: When a bus monitor circuit 161 detects FRAME# and IRDY# being both supported and a bus request detecting circuit 162 and a system event detecting circuit 163 detect a bus request signal and a system event signal not being generated, the output of a 3-input OR gate 164 goes down to 'L' indicating that the bus is not in operation. Consequently, a clock control signal output circuit 165 generates a clock control signal indicating the stop of PCICLK, and consequently the supply to PCICLK to respective PCI devices is stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a computer system, and more particularly to a computer system having a bus clock control function.

[0002]

2. Description of the Related Art Conventionally, an ISA (Industry) is used as a system bus for a personal computer.
The standard architectural (EISA) bus and the EISA (extended ISA) bus have been the mainstream. Recently, however, in order to increase the data transfer speed and to construct a system architecture independent of a processor, a PCI (Peripheral Component) is used.
nt Interconnect buses are beginning to be adopted.

[0003] In the PCI bus, almost all data transfer is based on block transfer, and each of these block transfers is realized using burst transfer. As a result, a maximum data transfer rate of 133 Mbytes / sec (when the data bus has a 32-bit width) can be realized on the PCI bus.

Therefore, when the PCI bus is adopted,
Data transfer between I / O devices and between a system memory and an I / O device can be performed at high speed, and system performance can be improved.

In such a PCI bus architecture, a relatively high-speed bus clock of 33 MHz is used for realizing high-speed operation. This bus clock is for providing the timing of a transaction on the PCI bus to each peripheral device on the bus, and is always supplied to the peripheral devices on the bus during system operation.

[0006]

However, such a high-speed bus clock is one of the major factors that increase the power consumption of a computer. For this reason, recently, PCI
A specification for stopping the bus clock (“CLKRUN” protocol) has been included in the bus specification.

However, in order to implement the "CLKRUN" protocol in a system, all devices on the PCI bus need to have a function to support the "CLKRUN" protocol. Therefore, "CL
If there is an existing peripheral device that does not support the “KRUN” protocol, the “CLKRUN” protocol cannot be used, and the bus clock cannot be stopped.

The present invention has been made in view of such a point, and enables a bus clock to be controlled without implementing a special function such as a "CLKRUN" protocol in a peripheral device, thereby easily reducing power consumption. It is an object of the present invention to provide a computer system capable of achieving the following.

[0009]

SUMMARY OF THE INVENTION A computer system according to the present invention includes a plurality of peripheral devices coupled to a bus of a computer system, and a bus clock for giving the plurality of peripheral devices timing of transactions on the bus. Bus clock generating means for generating, a bus idle detecting means for monitoring transactions on the bus and detecting whether or not the bus is idle, and an event for detecting the presence or absence of a bus request signal and an interrupt signal from each of the peripheral devices Detection means, and clock control means for controlling a clock generation operation of the bus clock generation means based on detection results of the bus idle detection means and the event detection means, wherein a bus idle state is detected, and Generates the bus request signal and the interrupt signal Is it not is characterized by comprising a clock control means for stopping the bus clock when detected.

In this computer system, the system state is checked by detecting the presence or absence of a bus idle state, a bus request signal and an interrupt signal, and the computer system is in a bus idle state and no bus request signal and no interrupt signal are generated. Is detected, it is determined that the system is idle, and the bus clock is stopped. In this case, even in the bus idle state, the bus clock is not stopped as long as the bus request signal or the interrupt signal is generated, so that the operation of the peripheral device is not affected. Therefore, unnecessary bus clocks can be stopped without implementing a special function such as the “CLKRUN” protocol in the peripheral device, and power consumption can be reduced.

[0011] The clock control means may control the bus clock after a lapse of a predetermined time from the detection of the bus idle state and the detection that the bus request signal and the interrupt signal are not generated. It is preferable to include means for delaying the timing of stopping the bus clock so that the bus clock is stopped.

If the bus clock is stopped immediately when the system is idle, even if an interrupt signal or the like is generated thereafter, it takes time until the supply of the bus clock is restarted, resulting in a decrease in system performance.
Therefore, in order to prevent a decrease in system performance, it is necessary to collectively execute as many processes as possible during the clock supply period, and this can be realized by delaying the timing of stopping the bus clock. .

Further, the computer system of the present invention has a plurality of devices coupled to a bus of the computer system, and a bus clock generating means for generating a bus clock for giving a timing of a transaction on the bus to the plurality of devices. Bus idle detecting means for monitoring a transaction on the bus and detecting whether or not the bus is idle; event detecting means for detecting the presence or absence of a bus request signal and an interrupt signal from each of the devices; Clock control means for controlling a clock generation operation of said bus clock generation means based on a detection result of said detection means and said event detection means, wherein a bus idle state is detected, and said bus request signal and said interrupt signal Has not been detected Characterized by comprising a clock control means for decreasing the frequency of the feeder the bus clock.

According to this configuration, instead of completely stopping the bus clock, the frequency of the bus clock is reduced. Normally, peripheral devices are configured so that even when the bus clock is stopped, some internal logic can operate, and there is no problem because interrupt signals and bus request signals can be generated normally. Some peripheral devices cannot operate at all if the bus clock is stopped. Therefore, when such devices are connected, it is necessary not to completely stop the bus clock, but to supply the minimum necessary clock to guarantee the operation of the devices. This makes it possible to reduce the power consumption while guaranteeing the operation of the device.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a computer system according to an embodiment of the present invention.
This computer system is a notebook-type or laptop-type portable computer that can be driven by a battery, and includes a processor bus 1, a PCI bus 2, an ISA bus 3, and a CPU 1 on its system board.
1, host-PCI bridge device 12, main memory 13,
Various PCI peripheral devices 14, 15, bus clock control circuit 16, bus clock generation circuit 17, PCI-ISA
Bridge device 18 and various ISA peripheral devices 1
9, 20, etc. are provided.

Of these components, PCI bus 2
That function as a PCI device connected to the host device, that is, a host-PCI bridge device 12, various PCI peripheral devices 14, 15, a PCI-ISA bridge device 18
Includes the P generated by the bus clock generation circuit 17.
A CI bus clock (PCICLK) is supplied. The PCI bus clock (PCICLK) gives the timing of a bus transaction to each PCI device, and all the cycles on the PCI bus 2 are performed by the PCI bus.
It is executed in synchronization with the bus clock (PCICLK).

Next, the function and configuration of each component shown in FIG. 1 will be described. The CPU 11 is realized by, for example, a microprocessor “Pentium” manufactured and sold by Intel Corporation in the United States. The processor bus 1 directly connected to the input / output pins of the CPU 11 has a 64-bit data bus. The main memory 13 is a memory device that stores an operating system, a device driver, an application program to be executed, processing data, and the like, and includes a plurality of DRAM modules.

The host-PCI bridge device 12 is a bridge LS connecting between the processor bus 1 and the PCI bus 2.
I, which functions as one of the bus masters of the PCI bus 2. The host-PCI bridge device 12 has a function of bidirectionally converting a bus cycle including data and addresses between the processor bus 1 and the PCI bus 2 and a function of controlling access to the main memory 13 via the memory bus. And so on.

The PCI bus 2 is a clock synchronous type input / output bus. As described above, all cycles on the PCI bus 2 are performed in synchronization with the PCI bus clock. PC
The frequency of the I bus clock is 33 MHz at the maximum. PC
The I bus 2 has an address / data bus used in a time-division manner. This address / data bus is 32 bits wide.

The data transfer cycle on the PCI bus 2 is
It consists of an address phase and one or more data phases following it. In the address phase, an address and a transfer type are output, and in the data phase, 8-bit, 16-bit, 24-bit or 32-bit data is output.

The PCI devices 14 and 15 are, for example, a graphics controller, a PC card (card bus) controller, an IrDA controller, a SCSI controller, and the like, and function as a bus master of the PCI bus 2 like the host-PCI bridge device 12.

The PCI-ISA bridge device 16 is a PC
This is a bridge LSI that connects the I bus 2 and the ISA bus 3, and functions as one of the PCI devices. The ISA devices 19 and 20 on the ISA bus 3 are, for example, HD
D, a system timer, a keyboard controller, and the like.

The bus clock control circuit 16 controls the suspension / resumption of the supply of the PCI bus clock (PCICLK) to each PCI device.
Stop / restart of the I bus clock (PCICLK) is controlled based on a bus idle signal, a bus request signal, and a system event signal. The bus idle signal indicates the operating state of the PCI bus 2, that is, whether or not the bus is operating (bus cycle is being executed). The bus request signal is a signal for the bus master to request the PCI bus arbiter to use the PCI bus 2. The system event signal indicates that an event such as an interrupt signal has occurred in the system.

The bus clock control circuit 16 detects the idle of the PCI bus due to the bus idle signal, and if there is no bus request signal and no system event signal, controls the bus clock generation circuit 17 by the clock control signal to change the bus clock. Stop. When a bus request signal or a system event signal is generated while the bus clock is stopped, the bus clock control circuit 16 controls the bus clock generation circuit 17 by the clock control signal to restart the supply of the bus clock.

FIG. 2 shows a specific configuration example of the bus clock control circuit 16. As illustrated, the bus clock control circuit 16 includes a bus monitoring circuit 161, a bus request detection circuit 162, a system event detection circuit 163, an OR
Gate 164 and clock control signal output circuit 165
It is composed of

The bus monitoring circuit 161 is for generating the above-mentioned bus idle signal, and executes a transaction on the PCI bus 2 using the frame signal FRAME # and the initiator ready signal IRDY # defined on the PCI bus 2. It monitors and asserts the bus idle signal to an "H" level when detecting that the bus is not operating, and deasserts the bus idle signal to an "L" level when detecting that the bus is operating.

Here, FRAME # is a signal driven by the current master to indicate the start and duration of a transaction. When FRAME # is deasserted, it indicates that the transaction is the last data phase. IRDY # is a signal driven by the current master, and in a write cycle,
Asserted to indicate that the master has output committed data on the bus, and in a read cycle, is asserted to indicate that the master is ready to receive data.

When both FRAME # and IRDY # are deasserted, the bus monitor circuit 161 detects that the bus is idle, and asserts the bus idle signal to the "H" level.

The bus request detection circuit 162 monitors all the bus request signals REQ1 # to REQn # input from each PCI device to the PCI bus arbiter.
When any of REQ1 # to REQn # is asserted, the bus request signal is asserted to "H" level.

The system event detection circuit includes an interrupt signal INTA-D input from each PCI device to the interrupt controller, an interrupt signal IRQ0-15 input from each ISA device to the interrupt controller, a non-maskable interrupt signal NMI, a system management The interrupt signal SMI is monitored, and when any interrupt signal is generated, the system event signal is asserted to "H" level.

The bus idle signal from the bus monitor circuit 161 is inverted and input to the first input of a three-input OR gate 164. Further, the bus request signal and the system event signal from the bus request detection circuit 162 and the system event detection circuit 163 are directly input to the second input and the third input of the three-input OR gate 164, respectively. The output of 3-input OR gate 164 is in bus operation ("H" level)
/ Shows that the bus is not operating (“L” level) and is input to the clock control signal output circuit 165.

Clock control signal output circuit 165 generates a clock control signal for instructing stop / restart of PCICLK based on the output of three-input OR gate 164. Next, the operation of this embodiment will be described with reference to FIGS.

The timing chart of FIG. 3 shows the timing when the bus clock (PCICLK) is stopped. That is, when it is detected that both FRAME # and IRDY # are deasserted, and it is detected that the bus request signal and the system event signal are not generated, the output of the 3-input OR gate 164 indicates that the bus is not operating. "L" level shown in FIG. As a result, a clock control signal instructing the stop of PCICLK is generated from the clock control signal output circuit 165.
The supply of PCICLK to the device is stopped.

If a clock request signal is generated during the PCICLK supply suspension period (detection of assertion of FRAME # or IRDY # by the bus monitoring circuit 161)
The detection of the generation of the bus request signal by the bus request detection circuit 162 or the detection of the generation of the interrupt signal by the system event detection circuit 163) The output of the three-input OR gate 164 becomes "H" level indicating that the bus is operating. Thereby, the PCICL is output from the clock control signal output circuit 165.
A clock control signal for instructing restart of K is generated, whereby the supply of PCICLK to each PCI device is restarted.

As described above, according to the configuration of FIG. 2, the system state is checked by detecting the presence or absence of the bus idle state, the bus request signal and the interrupt signal, and in the bus idle state, the bus request signal and the interrupt signal Is detected, it is determined that the system is idle, and PCICLK is stopped. In this case, even if the bus is idle, the PCICLK is not stopped as long as the bus request signal or the interrupt signal is generated, so that the operation of each PCI device is not affected. If a bus request signal or an interrupt signal is generated from the PCI device while the PCICLK is stopped, the supply of the PCICLK is restarted,
A normal bus transaction synchronized with CICLK can be performed. Therefore, "CL"
Unnecessary bus clocks can be stopped without implementing a special function such as a RUN protocol, and power consumption can be reduced.

FIG. 5 shows a second configuration example of the bus clock control circuit 16. Here, a snap timer 166 is provided in addition to the configuration of FIG. The snap timer 166 is for delaying the stop timing of the PCICLK for a certain period of time, and starts the count operation after the output of the three-input OR gate 164 becomes “L” level indicating that the bus is not operating. When the count value has been reached, it is notified to the clock control signal output circuit 165. As a result, the clock control signal instructing the stop of the PCICLK is generated with a delay of the count time of the snap timer 166. Snap timer 16
6, the count value of the bus clock control circuit 16
A configuration register for setting a counter value is provided therein, and a counter value corresponding to a desired delay time is set therein by software, thereby making the counter programmable.

FIG. 6 shows the bus clock control circuit 1 of FIG.
6 shows a state transition. In FIG. 6, a state S1 (RUN) indicates a state in which PCICLK is being supplied.
2 (SNAP). In the state S2 (SNAP), the count operation of the snap timer 166 is performed.
When the generation of an interrupt signal or the generation of a bus request signal is detected during the count operation of the snap timer 166, the state S1
(RUN) and the snap timer 166
Is returned to the initial value. On the other hand, state S2 (S
When the counting operation of the snap timer 166 is completed in (NAP), the process proceeds to a state S3 (STOP). In the state S3 (STOP), the supply of the PCICLK is stopped. When the occurrence of an interrupt signal or the occurrence of a bus request signal is detected in the state S3 (STOP), the state S1 (R
UN).

FIG. 7 shows the operation timing when a transition is made from state S1 (RUN) to state S3 (STOP) via state S2 (SNAP). That is, FR
When it is detected that AME # and IRDY # are both deasserted and that no bus request signal and no system event signal are generated, a three-input OR
The output of gate 164 attains an "L" level indicating that the bus is not operating. Thus, the counting operation of the snap timer 166 is started. PCICLK continues to be supplied until the count operation is completed. When the count operation is completed, the clock control signal output circuit 165 outputs P
A clock control signal for instructing stop of CICLK is generated.
The supply of K is stopped.

If the PCICLK is stopped immediately when the bus is idle, even if an interrupt signal or the like is generated thereafter, it takes time until the supply of the PCICLK is restarted, thereby deteriorating the system performance. Therefore, as in the present embodiment, the stop timing of the PCICLK is delayed for a certain period by the count operation of the snap timer 166, so that the system performance can be prevented from deteriorating. It can be executed.

Also, some PCIs require several clocks from the completion of a bus transaction to the occurrence of the next event.
The use of 6 makes it possible to immediately respond to a bus request signal or an interrupt signal from such a device.

It should be noted that, in the above description, P
Although only an example in which the CICLK is stopped has been described, power consumption can be reduced even if the PCICLK is continuously supplied in a state where the frequency is lowered instead of stopping the PCICLK. FIG. 8 shows the operation timing in this case.

That is, FRAME # and IRDY #
Are deasserted together, and it is detected that the bus request signal and the system event signal are not generated, the output of 3-input OR gate 164 attains an "L" level indicating that the bus is not operating. . As a result, a clock control signal is intermittently generated from the clock control signal output circuit 165 in order to reduce the frequency of PCICLK, whereby the PC supplied to each PCI device is
The frequency of ICLK is reduced by a factor. When a clock request signal is generated during such a slow clock operation (detection of assertion of FRAME # or IRDY # by the bus monitoring circuit 161 and the bus request detection circuit 162
Detection of the occurrence of a bus request signal or detection of the occurrence of an interrupt signal by the system event detection circuit 163). The output of the three-input OR gate 164 goes to "H" level indicating that the bus is operating. As a result, the clock control signal output circuit 165 generates a clock control signal for instructing the restart of the PCICLK, whereby the frequency of the PCICLK supplied to each PCI device is returned to the original frequency.

The slow clock control is used in combination with the snap timer 166 shown in FIG.
The frequency of LK may be lowered.

A normal PCI device is configured so that some internal logic can operate even when the bus clock is stopped, and can normally generate an interrupt signal and a bus request signal. However, some PCI devices cannot operate at all if the bus clock is stopped. Therefore,
When such a device is connected, as described above, instead of completely stopping the bus clock,
It is preferable to supply the minimum necessary clock to ensure the operation of these devices. This makes it possible to reduce the power consumption while guaranteeing the operation of the device.

[0045]

As described above, according to the present invention, the system state is examined by detecting the presence or absence of the bus idle state, the bus request signal and the interrupt signal, and the stop / restart of the bus clock is controlled accordingly. By doing so, unnecessary bus clocks can be stopped without implementing a special function such as the “CLKRUN” protocol in the PCI device, and power consumption can be reduced. In particular, by using the snap timer and controlling the bus clock frequency, it is possible to improve system performance and realize power saving independent of the type of PCI device.

[Brief description of the drawings]

FIG. 1 is an exemplary block diagram showing the configuration of a computer system according to an embodiment of the present invention.

FIG. 2 is an exemplary view showing an example of the configuration of a bus clock control circuit provided in the system of the embodiment.

FIG. 3 is a timing chart showing a clock stop operation using the bus clock control circuit of FIG. 2;

FIG. 4 is a timing chart showing a clock restart operation using the bus clock control circuit of FIG. 2;

FIG. 5 is an exemplary view showing a second configuration example of the bus clock control circuit provided in the system of the embodiment;

FIG. 6 is a diagram showing a state transition of the bus clock control circuit of FIG. 5;

FIG. 7 is a timing chart showing a clock stop operation using the bus clock control circuit of FIG. 5;

FIG. 8 is a timing chart showing an operation of a bus clock frequency lowering process realized by using the bus clock control circuit of FIG. 2 or 5;

[Explanation of symbols]

 2 PCI bus 3 ISA bus 11 CPU 12 Host-PCI bridge 13 Memory 14 15 PCI peripheral device 16 Bus clock control circuit 17 Bus clock generation circuit 18 PCI-DS bridge 161 Bus monitoring circuit 162 bus request detection circuit 163 system event detection circuit 166 snap timer

Claims (4)

[Claims] A plurality of peripheral devices coupled to a bus of a computer system; bus clock generating means for generating a bus clock for giving a timing of a transaction on the bus to the plurality of peripheral devices; Bus idle detection means for monitoring whether or not a bus idle state is detected; an event detection means for detecting the presence or absence of a bus request signal and an interrupt signal from each of the peripheral devices; A clock control unit that controls a clock generation operation of the bus clock generation unit based on a detection result of an event detection unit, wherein the clock control unit detects a bus idle state and generates the bus request signal and the interrupt signal. Bus clock is stopped when it is detected that Computer system characterized by comprising a clock control means for. 2. The system according to claim 1, wherein the clock control unit is configured to output the bus clock after a lapse of a predetermined time since the bus idle state is detected and the bus request signal and the interrupt signal are not generated. Means for delaying the timing of stopping the bus clock so as to be stopped, and restarting the supply of the bus clock when the release of the bus idle state or the occurrence of the bus request signal or the interrupt signal is detected. 2. The computer system according to claim 1, further comprising: 3. A plurality of devices coupled to a bus of a computer system, bus clock generating means for generating a bus clock for giving a timing of a transaction on the bus to the plurality of devices, and a transaction on the bus Bus idle detection means for monitoring whether or not a bus idle state is detected, an event detection means for detecting the presence or absence of a bus request signal and an interrupt signal from each of the devices, the bus idle detection means and the event detection means Clock control means for controlling the clock generation operation of the bus clock generation means based on the detection result of the above, wherein it is detected that the bus idle state is detected and the bus request signal and the interrupt signal are not generated. When detected, the frequency of the bus clock is reduced. Computer system characterized by comprising a that clock control means. 4. The clock control unit according to claim 1, wherein the clock control unit detects the bus idle state and detects that the bus request signal and the interrupt signal have not been generated, and after a lapse of a predetermined time, outputs the bus clock. Means for delaying the timing of reducing the frequency of the bus clock so that the frequency is reduced; and releasing the bus idle state, detecting the occurrence of the bus request signal or the interrupt signal, 4. The computer system according to claim 3, further comprising: means for returning a frequency to an original state.