JP2007148977A - Input/output processing device and computer system having same input/output processing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain an efficient operation following a bus clock from a clock generation output control means of a host system without requiring a mechanism for generating a special clock for an operation. <P>SOLUTION: An IO processing device 10 is connected with the host system 30 via a bus 20. The IO processing device 10 includes an IO processor 12 which is started by a starting request signal and operates by a clock generated by the bus clock BCLK and a bus clock control signal output control part 141. A clock generation output control part 31 of the host system 30 notifies the control part 141 of invalidation notice when the bus 20 is not used exceeding fixed time at a valid output state where an output operation of the bus clock BCLK is valid. The control part 141 requests continuation of the valid output state to a control part 31 within the fixed time if starting is requested by the starting request signal or the IO processor 12 is under operation when the invalidation notice is detected. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an input / output processing apparatus that is connected to a host system via a bus that operates on a bus clock and performs input / output processing between the input / output device and the host system, and a computer system having the input / output processing apparatus.

  A computer system represented by a personal computer generally has a bus that operates on a bus clock such as a PCI (Peripheral Component Interconnect) bus. A host system that uses various input / output devices (IO devices) is connected to the bus. An input / output processing device (IO processing device) incorporating a processor is also connected to the bus. The IO processing device operates by a bus clock and performs input / output processing between the IO device and the host system.

  Usually, the host system has a clock generation output control unit that controls generation and output of a bus clock. This clock generation output control unit generates a bus clock only when the host system needs to access the IO device via the IO processing device. The generated bus clock is sent to the bus. The I / O processing device is operated by the bus clock on this bus. Further, the clock generation output control unit stops the output of the bus clock when the bus is not used for a certain period of time in order to save power of the computer.

  However, in an IO processing device, a state where a bus is not used for a certain time may occur due to processing convenience. In such a case, output of the bus clock is stopped by the clock generation output control unit, so that the IO processing device (such as a processor built in the IO processing device) cannot continue its operation.

  Therefore, the conventional IO processing device has a clock generation control unit unique to the IO processing device. The clock generation control unit generates a clock (operation clock) necessary for the operation of the processor or the like, for example, according to the operation state of the processor. With this operation clock, the processor or the like built in the IO processing device can continue the operation. However, in such a conventional technique, when a plurality of IO processing devices are connected to a host system via a bus, it is necessary to provide a clock generation control unit in each of the plurality of IO processing devices.

Therefore, Patent Document 1 discloses a host system (computer system) having a bus clock control circuit. This bus clock control circuit monitors transactions on the bus and bus request signals and interrupt signals from each IO processing device, and controls the generation and output of the bus clock based on the monitoring results. Specifically, the bus clock control circuit stops the bus clock when the bus is in an idle state (bus idle state) and the bus request signal and the interrupt signal are not asserted. In other words, even in the bus idle state, the bus clock is not stopped as long as the bus request signal or the interrupt signal is asserted. In this case, the IO processing device that is asserting the bus request signal or the interrupt signal can continue the operation.
JP 11-53049 A (paragraphs 0009-0010)

  As described above, the bus clock control circuit described in Patent Document 1 can control the generation and output of the bus clock necessary for the operation of each IO processing device. For this reason, each IO processing device does not require a mechanism (clock generation control unit) for generating a special clock for operation.

  Instead, the bus clock control circuit (clock generation output control means) has a special mechanism for monitoring transactions on the bus and bus request signals and interrupt signals from each IO (input / output) processing device (that is, the bus). A special mechanism for monitoring).

  The present invention has been made in consideration of the above circumstances, and its purpose is not to require a mechanism for generating a special clock for operation, and to provide a clock generation output control means of the host system for a special purpose for bus monitoring. It is an object of the present invention to provide an input / output processing apparatus and a computer system having the input / output processing apparatus that can perform an efficient operation according to the bus clock from the clock generation output control means.

  According to one aspect of the present invention, an input / output device is connected to the host system via a bus operating with a bus clock output by a clock generation output control unit of the host system. An input / output processing device that performs output processing is provided. The input / output processing device is operated by a processor clock for performing input / output between the input / output device and the bus, and operates the input / output control means by an instruction execution operation according to a program. When the instruction execution operation is stopped, an active stop state signal indicating that the input / output processor is in a stop state is output, and start-up is requested by an active start request signal in the stop state. An input / output processor that resumes the instruction execution operation and deactivates the stop state signal; and inputs the bus clock, generates the processor clock based on the bus clock, and outputs the processor clock to the input / output Processor clock control means for outputting to a processor, the input / output processor Therefore, when the active stop state signal is output, the output of the processor clock is stopped, and when start is requested by the start request signal in the stop state of the output of the processor clock, the processor clock to the input / output processor is output. Processor clock control means for resuming the output of the bus, and requesting the continuation of an effective output state in which the output operation of the bus clock by the clock generation output control means is valid according to the states of the input / output processor and the clock generation output control means Bus clock control requesting means. The bus clock control requesting means detects the bus generation output as a result of detecting that the bus is not used beyond a predetermined time by the clock generation output control means in a valid output state in which the bus clock output operation is valid. An invalid notice detection means for detecting an invalid notice for notifying that the output operation of the bus clock outputted by the control means is invalidated, and when the invalid notice is detected, activation is requested by the activation request signal. If the inactive stop state signal is output by the input / output processor, a valid request response that requests the clock generation output control means to continue the valid output state within a predetermined time Means.

  According to the present invention, the input / output processing device can operate only by the bus clock without requiring a mechanism for generating the operation clock unique to the processing device, and can control the clock generation and output of the host system. An efficient operation according to the bus clock from the clock generation output control means can be performed without providing the means with a special mechanism for bus monitoring.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of a computer system including an IO processing device according to an embodiment of the present invention. This computer system is realized as a notebook personal computer, for example.

  In FIG. 1, an IO processing device 10 is connected to a host system 30 by a bus 20 that operates on a bus clock BCLK, such as a PCI bus. The host system 30 uses the IO device 40 via the IO processing device 10. The IO processing device 10 operates by the bus clock BCLK and performs input / output processing between the IO device 40 and the host system 30.

  The IO processing device 10 includes an IO control unit 11, an IO processor 12, a processor clock control unit 13, and a clock / processor control unit 14. The IO control unit 11 performs data input / output between the IO device 40 and the bus 20. The IO processor 12 operates in accordance with the processor clock 130 and executes instructions according to a program. The IO processor 12 performs an operation for input / output by the IO control unit 11 by this instruction execution operation. The IO processor 12 has a function of stopping / resuming the instruction execution operation. When the instruction execution operation is stopped, the IO processor 12 outputs an active stop state signal 120 of, for example, logic “1” indicating that the IO processor 12 is in a stop state of the instruction execution operation. The IO processor 12 resumes the instruction execution operation when an active start request signal 140 of, for example, logic “1” is input while the instruction execution operation is stopped. When the stop state signal 120 is logic “0” (inactive), it indicates that the IO processor 12 is operating. In this embodiment, the logic value of the binary signal is uniquely determined depending on whether the signal is at a high level or a low level, regardless of whether the signal applies positive logic or negative logic. Yes. Here, the logical value of the binary signal is determined to be “1” when the level is high and “0” when the level is low.

  The processor clock controller 13 receives the bus clock BCLK and generates the processor clock 130 based on the bus clock BCLK. The processor clock 130 is output to the IO processor 12 by the processor clock control unit 13 as an operation clock (operation clock) for the IO processor 12. The processor clock control unit 13 stops the output of the processor clock 130 to the IO processor 12 when the stop state signal 120 of logic “1” is output from the IO processor 12. Thereby, power saving in the IO processing device 10 is achieved. The processor clock control unit 13 resumes the output of the processor clock 130 to the IO processor 12 when the activation request signal 140 of logic “1” is input while the output of the processor clock 130 is stopped.

  The host system 30 has a clock generation output control unit 31. The clock generation output control unit 31 generates the bus clock BCLK. The clock generation output control unit 31 is connected to the clock / processor control unit 14 of the IO processing device 10 by the bus clock control signal line 21. More specifically, the clock generation output control unit 31 is connected to a bus clock control signal output control unit 141 (to be described later) of the clock / processor control unit 14 through a bus clock control signal line 21.

  The bus clock control signal line 21 is a bidirectional single line. The bus clock control signal line 21 is used to transfer a bus clock control signal that can be input and output by both the clock generation output control unit 31 and the bus clock control signal output control unit 141. Both outputs of the control units 31 and 141 are wired-ORed by, for example, negative logic by the bus clock control signal line 21. Here, the inactive bus clock control signal of logic “1” is transmitted on the bus clock control signal line 21 only when both of the control units 31 and 141 output the inactive bus clock control signal of logic “1”. Is transferred. When at least one of the control units 31 and 141 outputs an active bus clock control signal of logic “0”, an active bus clock control signal of logic “0” is transmitted on the bus clock control signal line 21. Transferred. The bus clock control signal on the signal line 21 can be input by both the clock generation output control unit 31 and the bus clock control signal output control unit 141.

  In the present embodiment, the control units 31 and 141 input the wired OR value by the bus clock control signal line 21 with respect to the output values of the control units 31 and 141. The wired OR value input by the control units 31 and 141 is nothing but the value (input value) of the bus clock control signal (input bus clock control signal) input from the bus clock control signal line 21 by the control units 31 and 141. Further, the output values of the control units 31 and 141 are regarded as the value (output value) of the bus clock control signal (output bus clock control signal) output from the control units 31 and 141 to the bus clock control signal line 21. Can do. As will be described later, the bus clock control signal has a bus clock BCLK output operation valid (valid output state), a bus clock BCLK output operation invalid (invalid output state), and a bus clock control signal. A notice that the output operation of the clock BCLK becomes invalid (invalid notice), a request to continue the output operation of the bus clock BCLK as a response to the invalid notice (continuation request for valid output state), and a bus clock as a response to the invalid notice Indicates one of the requests not to continue the output operation of BCLK.

  The clock generation output control unit 31 has a function of performing bus clock generation output control including an output operation for generating and outputting the bus clock BCLK based on the use state of the bus 20 and the input / output values of the bus clock control signal. Details of the function of the clock generation output control unit 31 will be described with reference to the state transition diagram of FIG.

  The clock generation output control unit 31 has three valid output states (bus clock valid output state) ST1, invalid notice output state (bus clock invalid notice output state) ST2, and bus clock invalid output state (bus clock valid output state) ST3. Can take state.

  First, the valid output state ST1 indicates that the clock generation output control unit 31 is in a state for outputting the bus clock BCLK to enable the bus 20. In this state ST1, the clock generation output control unit 31 sets the output of the control unit 31 to a low level (logic “0”), thereby changing the bus clock control signal on the bus clock control signal line 21 to a low level (logic “0”). 0 ”). This active bus clock control signal of logic “0” indicates that the output operation of the bus clock BCLK by the clock generation output control unit 31 is valid (that is, the valid output state). As described above, the clock generation output control unit 31 functions as valid output notification means for notifying the bus clock control signal output control unit 141 of the valid output state in the valid output state ST1.

  In the valid output state ST1, the bus 20 is generally in a used state (a state in which the bus is in use). In the valid output state ST1, the clock generation output control unit 31 also functions as a bus non-use state detecting unit, and detects that the bus 20 is not used for a certain time (bus non-use state). When the bus non-use state is detected in the valid output state ST1, the clock generation output control unit 31 transits from the valid output state ST1 to the invalid notice output state ST2.

  In the invalid notice output state ST2, the clock generation output control unit 31 functions as an invalid notice unit and switches the output (output value) of the control unit 31 from logic “0” to logic “1”. Then, the bus clock control signal on the bus clock control signal line 21 is switched from logic “0” (low level) to logic “1” (high level), that is, from active to inactive. As a result, the bus clock control signal output control unit 141 is notified that the output operation of the bus clock BCLK will become invalid in the near future (that is, the bus clock is invalid). This notification is referred to as invalid notice (bus clock invalid notice). In the invalid notice state ST2, the clock generation output control unit 31 continues the operation of outputting the bus clock BCLK. That is, the output operation of the bus clock BCLK is still effective.

  When the bus clock control signal line 21 becomes logic “1”, the bus clock control signal output control unit 141 sets the output value of the control unit 141 to logic “0”, whereby the bus on the bus clock control signal line 21 is set. The clock control signal can be set to logic “0” (active). The active bus clock control signal of logic “0” on the bus clock control signal line 21 in the invalid notice state ST2 continues the operation of outputting the bus clock BCLK to the clock generation output control unit 31 (continuation of the valid output state). Indicates that you are requesting. This request is called a valid request (bus clock valid request). On the other hand, the inactive bus clock control signal of logic “1” on the bus clock control signal line 21 in the invalid notice state ST2 does not require the continuation of the output operation of the bus clock BCLK, that is, a valid request (bus clock valid request). ) Indicates none.

  When the clock generation output control unit 31 transits to the invalid notice state ST2 and notifies the bus clock control signal output control unit 141 of the invalid notice, it functions as a valid request detection unit. When the clock generation output control unit 31 inputs a low-level (logic “0”) bus clock control signal indicating that there is a valid request within a certain time after transitioning to the invalid notice state ST2, and detects that there is a valid request Return to the effective output state ST1. Then, the clock generation output control unit 31 switches the output value of the control unit 31 to the logic “0”, thereby replacing the bus clock control signal output control unit 141 with the bus clock control signal on the bus clock control signal line 21. Maintain logic "0". An active bus clock control signal of logic “0” in this state indicates that the bus clock is valid. When the output value of the control unit 31 is switched to logic “0”, the clock generation output control unit 31 continues the output operation (valid output state) of the bus clock BCLK.

  On the other hand, if the logic “0” bus clock control signal indicating that there is a valid request is not input within a certain time after the transition to the invalid notice state ST2, the clock generation output control unit 31 starts from the invalid notice state ST2 to the invalid output state. Transition to ST3. In other words, after the transition to the invalid notice state ST2, the clock generation output control unit 31 detects that there is no valid request if the bus clock control signal of logic “1” continues to be input even after a certain time has elapsed. The bus clock control signal is changed to the invalid output state ST3 while maintaining the logic “1”. In this state ST3, the clock generation output control unit 31 stops the operation of outputting the bus clock BCLK while maintaining the bus clock control signal at logic “1”. Thereby, power saving of the computer system of FIG. 1 is realized. The bus clock control signal of logic “1” in the invalid output state ST3 indicates that the output operation of the bus clock BCLK is invalid (bus clock output invalid).

  The clock generation output control unit 31 functions as a bus use start detection unit in the invalid output state ST3, and detects that the host system 30 is about to start using the bus 20 (that is, a bus use start request). When the clock generation output control unit 31 detects the bus use start request of the host system 30, the clock generation output control unit 31 transits from the invalid output state ST3 to the valid output state ST1. Then, the clock generation output control unit 31 functions as valid output notification means again. That is, the clock generation output control unit 31 switches the output value of the control unit 31 to logic “0”, thereby changing the bus clock control signal on the bus clock control signal line 21 to logic “0” indicating that the bus clock is valid. It is set again and the output operation of the bus clock BCLK is resumed. As a result, the host system 30 can use the bus 20.

  The output value of the clock generation output control unit 31, the output value of the bus clock control signal output control unit 141, the logical value of the bus clock control signal on the bus clock control signal line 21, and the state of the bus clock BCLK (the bus clock The correspondence relationship between the output state) and the state of the clock generation output control unit 31 is shown in FIG. The bus clock control signal on the bus clock control signal line 21, that is, the wired OR result for the output values of the control units 31 and 141 is input to the control units 31 and 141. Therefore, the logical value of the bus clock control signal on the bus clock control signal line 21 is called the input value of the bus clock control signal or the input value of the wired OR result.

  Referring again to FIG. 1, the clock / processor control unit 14 includes a bus clock control signal output control unit 141, a setting register 142, and a control register 143. Both the registers 142 and 143 are operated by the host system 30 via the bus 20.

  The setting register 142 is used to hold correspondence setting information for designating correspondence with respect to the input / output of the bus clock control signal to the bus clock control signal output control unit 141. In the present embodiment, the correspondence setting information is 1-bit information, and the setting register 142 is a 1-bit register.

The setting value of the setting register 142 (value of the corresponding setting information) is “corresponding invalid” when the logic is “0” (first value), and “corresponding valid” when the logic is “1” (second value). Is shown.
“Correspondence invalid” means that the bus clock control signal output control unit 141 is designated to have no influence on the clock generation output control unit 31 with respect to the bus clock control signal. Specifically, “correspondence invalid” is set to a value that always indicates that there is no bus clock valid request for the output of the bus clock control signal output control unit 141 (that is, the output of the bus clock control signal). Indicates to do. On the other hand, regarding the input of the bus clock control signal, “correspondence invalid” indicates that the bus clock control signal output control unit 141 is not concerned. Therefore, “correspondence invalid” also means that the request for continuation of the valid output state for the invalid notice from the clock generation output control unit 31 is always suppressed.

  On the other hand, “correspondence valid” means an operation determined by a combination of the set value of the control register 143 and the value (input value) of the stop state signal 120 with respect to input / output of the bus clock control signal. This indicates what the unit 141 does. The operation of the bus clock control signal output control unit 141 will be described later.

  The control register 143 is used to hold activation request control information for controlling activation of the IO processor 12 of the IO processing device 10 from the host system 30. In the present embodiment, the activation request control information is 1-bit information, and the control register 143 is a 1-bit register.

  The setting value of the control register 143 (the value of the activation request control information) is “no activation request” when the logic is “0” (first value), and “no” when the logic is “1” (second value). Indicates that there is a startup request. “No activation request” indicates that the activation request signal 140 for requesting activation of the IO processor 12 is made inactive (logic “0”). On the other hand, “with activation request” indicates that the activation request signal 140 is activated (logic “1”). In this embodiment, the output (1-bit output) of the control register 143 is used as the activation request signal 140. That is, the control register 143 is used as an activation request signal output unit.

  The bus clock control signal output control unit 141 is a bus clock for requesting validity / invalidity of the output operation of the bus clock BCLK by the clock generation output control unit 31 according to the state of the IO processor 12 and the clock generation output control unit 31. It functions as a control request means. The bus clock control signal output control unit 141 has a function of always setting the output value of the control unit 141 to logic “1” indicating that no bus clock is requested when the setting register 142 sets “corresponding invalid”. Have Further, the bus clock control signal output control unit 141 functions as an invalid notice detection unit in a state in which “correspondence valid” is set by the setting register 142. Further, the bus clock control signal output control unit 141 functions as a valid request response means when the invalid notice is detected from the clock generation output control unit 31 in the state where “correspondence valid” is set and the invalid notice is detected. . In this case, the bus clock control signal output control unit 141 sets the output value of the control unit 141 to logic “0” indicating that a bus clock valid request is present or the bus clock valid within a certain time according to the state of the stop state signal 120. Set to logic "1" indicating no request.

Next, details of the function of the bus clock control signal output control unit 141 will be described with reference to the state transition diagram of FIG.
First, the first no valid request state ST11 shows a state in which the bus clock control signal output control unit 141 sets the output value of the control unit 141 to logic “1” indicating no bus clock valid request. The first valid request-free state ST11 is classified into three states.

  The first is a state in which the bus clock control signal output control unit 141 is set to “corresponding invalid” by the setting register 142. In this first state, the bus clock control signal output control unit 141 does not respond to the bus clock control signal. That is, the bus clock control signal output control unit 141 has no knowledge of the bus clock control signal on the bus clock control signal line 21. The bus clock control signal output control unit 141 always sets the output value of the control unit 141 to logic “0” indicating that there is no bus clock valid request. Therefore, in the first state, even if the clock generation output control unit 31 notifies the bus clock control signal output control unit 141 of an invalid notice, the bus clock control signal output control unit 141 outputs an effective output to the clock generation output control unit 31. No continuation of state is required.

  The second is a state in which the bus 20 can be normally used. This second state corresponds to the effective output state ST1 of the clock generation output control unit 31. In this second state, the bus clock control signal output controller 141 is set to “correspondence valid” by the setting register 142. In the second state, the bus clock control signal output control unit 141 receives a valid input (valid bus clock control signal input) of an active bus clock control signal of logic “0” (low level) from the bus clock control signal line 21. Is in a state. In this second state, the output of the bus clock BCLK by the clock generation output control unit 31 is valid.

  The third is a state in which the bus 20 is stopped. This third state corresponds to the invalid output state ST3 of the clock generation output control unit 31. In the third state, the bus clock control signal output control unit 141 is set to “correspondence valid” by the setting register 142 as in the second state. In the third state, the bus clock control signal output control unit 141 receives an invalid input (invalid bus clock control signal input) that inputs an inactive bus clock control signal of logic “1” (high level) from the bus clock control signal line 21. ) State.

  Now, it is assumed that the bus clock control signal output control unit 141 is in the first state of the first no valid request state ST11. In this first state, 1-bit correspondence setting information of logic “0” indicating “correspondence invalid” is set in the setting register 142. In such a state, the clock generation output control unit 31 performs an output operation of the bus clock BCLK in order to make the bus 20 usable. Further, the clock generation output control unit 31 sets the output value of the control unit to logic “0” in order to indicate that the output operation of the bus clock BCLK is valid. In this case, the bus clock control signal on the bus clock control signal line 21 is set to logic “0”, and the clock generation output control unit 31 enters the valid output state ST1. In this state, the host system 30 can use the bus 20.

  Here, when the host system 30 accesses the setting register 142 included in the clock / processor control unit 14 of the IO processing device 10 via the bus 20, a logic indicating “correspondence valid” is displayed in the setting register 142. Assume that 1-bit correspondence setting information of “1” is set. Then, the bus clock control signal output control unit 141 enters the second state of the first valid request-free state ST11. Here, the bus clock control signal output control unit 141 functions as an invalid notice detection unit that detects an invalid notice from the clock generation output control unit 31.

  If the bus 20 is not newly used after a certain time has elapsed after the bus 20 has been used, the clock generation output control unit 31 transitions from the valid output state ST1 to the invalid notice state ST2. In this invalid notice state ST2, the clock generation output control unit 31 switches the value of the bus clock control signal on the bus clock control signal line 21 (the value of the wired OR result) from logic “0” to logic “1”. An invalid notice is given to the bus clock control signal output controller 141.

  Now, the bus clock control signal output control unit 141 for which “correspondence valid” is designated by the correspondence setting information set in the setting register 142 is set to the logic “from the bus clock control signal line 21 in the first valid request-free state ST11. Assume that a 1 "bus clock control signal is input. That is, it is assumed that the bus clock control signal output control unit 141 has received an invalid notice from the clock generation output control unit 31.

  Then, the bus clock control signal output control unit 141 detects the invalid notice and makes a transition from the no valid request state ST11 to either the valid request present state ST12 or the second valid request no state ST13.

  In this case, if the IO register 12 is in operation (the stop state signal 120 is logic “0”) even if the activation request is specified by the control register 143 or no activation request is specified, the bus clock The control signal output control unit 141 transits to a valid request state ST12. On the other hand, if no activation request is specified by the control register 143 and the IO processor 12 is stopped (the stop state signal 120 is logic “1”), the bus clock control signal output control unit 141 is valid. Transition to the no request state ST13.

  The bus clock control signal output control unit 141 functions as a valid request response unit that responds to the clock generation output control unit 31 with a valid request or with no valid request when transitioning to the valid request present state ST12 or the no valid request state ST13. To do.

  When the transition to the valid request state ST12 is made, the bus clock control signal output control unit 141 requests the value of the output of the control unit 141 (the output value of the bus clock control signal) to be valid within a certain time from the invalid notice input time. It is set to a value indicating the presence (logic “0”). That is, the bus clock control signal output control unit 141 outputs a response with a valid request in response to the invalid notice from the clock generation output control unit 31. Then, the bus clock control signal output control unit 141 returns to the first no-valid request state ST11 when a predetermined time has elapsed since the transition to the valid-request-withstanding state ST12.

  On the other hand, when the state transits to the second no valid request state ST13, the bus clock control signal output control unit 141 sets the output value (output value of the bus clock control signal) of the control unit 141 to a value (logical logic) indicating no valid request. “1”). That is, the bus clock control signal output control unit 141 outputs a response without a valid request in response to the invalid notice from the clock generation output control unit 31. The bus clock control signal output control unit 141 returns to the first no-valid request state ST11 after a predetermined time has elapsed since the transition to the second no-valid request state ST13.

  When the bus clock control signal output control unit 141 receives an invalid notice from the clock generation output control unit 31, the setting value of the setting register 142, the setting value of the control register 143, and the input value of the stop state signal 120 FIG. 5 shows the correspondence with the state of the bus clock control signal output control unit 141 (the output value of the bus clock control signal).

  Next, operations in the system of FIG. 1 will be described with reference to FIGS. Here, unless otherwise specified, it is assumed that the setting register 142 included in the clock / processor control unit 14 of the IO processing device 10 is set with 1-bit correspondence setting information of logic “1” indicating that the correspondence is valid.

  FIG. 6 shows a state where the bus clock BCLK output operation is valid (bus clock output valid), the IO processor 12 of the IO processing device 10 is operating, and the bus 20 has not been used for a certain time. 6 is a timing chart for explaining an operation when detected by a clock generation output control unit 31 of the host system 30.

  Now, the clock generation output control unit 31 of the host system 30 is in the valid output state ST1 in FIG. 2, and the bus clock control signal output control unit 141 of the IO processing device 10 is in the first no valid request state ST11 in FIG. It shall be in Here, it is assumed that the IO processor 12 is operating. That is, it is assumed that the bus clock control signal output control unit 141 is in the second state in the first valid request-free state ST11.

  In this state, the clock generation output control unit 31 performs the output operation of the bus clock BCLK in order to make the bus 20 usable. Further, the clock generation output control unit 31 sets the output value of the control unit to logic “0” in order to indicate that the output operation of the bus clock BCLK is valid (bus clock output valid). Thereby, the logical value of the bus clock control signal on the bus clock control signal line 21, that is, the wired OR result of the output value of the clock generation output control unit 31 and the bus clock control signal output control unit 141 by the bus clock control signal line 21 is obtained. The value is a logical “0”. In the following description, for simplification of expression, it is simply referred to as “wired-or result value”.

  The bus clock control signal output control unit 141 inputs the bus clock control signal (wired OR result) on the bus clock control signal line 21. As in this embodiment, when the input value is logic “0”, that is, when the bus clock BCLK is valid, the bus clock control signal output control unit 141 sets the output value of the control unit 141 to the logic “ It is maintained at 1 "to indicate no valid request.

  When the output operation of the bus clock BCLK is valid, the processor clock control unit 13 generates the processor clock 130 based on the bus clock BCLK and outputs the processor clock 130 to the IO processor 12. When access to the IO device 40 is requested by the host system 30, the IO processor 12 operates according to the processor clock 130 and executes instructions according to the program. The IO processor 12 performs an operation for input / output by the IO control unit 11 necessary for accessing the IO device 40 by this instruction execution operation. As a result, the IO control unit 11 executes data input / output between the IO device 40 and the bus 20 via the bus 20 in accordance with the bus clock BCLK.

  During the operation, the IO processor 12 outputs a stop state signal 120 of logic “0”. However, the IO control unit 11 does not always use the bus 20 while the IO processor 12 is operating. Here, it is assumed that the state where the bus 20 is not used continues for a certain time. As a result, the clock generation output control unit 31 detects the state where the bus 20 has not been used for a certain period of time in the valid output state ST1 (that is, the bus transaction is idle) at time t1 shown in FIG. And Then, the clock generation output control unit 31 transitions to the invalid notice state ST2 as shown in FIG.

  When the clock generation output control unit 31 transits to the invalid notice state ST2, the output value of the control unit 31 is changed from logic “0” to logic “1” for notice (invalid notice) that invalidates the output operation of the bus clock BCLK. To "". Then, the value of the bus clock control signal on the bus clock control signal line 21 (the value of the wired OR result) is switched from logic “0” to logic “1”.

  The bus clock control signal output control unit 141 receives the value of the bus clock control signal on the bus clock control signal line 21 (the value of the wired OR result), so that the clock generation output control unit 31 is notified of the invalid notice. Detect that. At this time, the bus clock control signal output control unit 141 is in the second state in the no-valid request state ST11. The IO processor 12 is operating (the stop state signal 120 is logic “0”), and the activation request signal 140 is logic “0” indicating that there is no activation request.

  The bus clock control signal output control unit 141 determines that the bus 20 is used by the IO control unit 11 when the invalid notice is detected in such a state, because the IO processor 12 is operating. In this case, the bus clock control signal output control unit 141 makes a transition to the valid request present state ST12, and sets the output value of the control unit 141 (the output value of the bus clock control signal) to logic “0” indicating that the bus clock valid request is present. Set to "". Then, the value of the bus clock control signal on the bus clock control signal line 21 (the value of the wired OR result) is switched from logic “1” to logic “0”.

  The clock generation output control unit 31 inputs a bus clock control signal value (wired OR result value) “0” on the bus clock control signal line 21, thereby requesting a valid request from the bus clock control signal output control unit 141. Detect that there is an indication. The clock generation output control unit 31 returns to the valid output state ST1 when detecting that there is a valid request within a certain time from the time t1 when the clock generation output control unit 31 transits to the invalid notice state ST2.

  When the clock generation output control unit 31 returns to the valid output state ST1, the output value of the control unit 31 (the output value of the bus clock control signal) is set to the bus clock valid again while the output operation of the bus clock BCLK is continued. Set to the value shown (logic "0"). On the other hand, the bus clock control signal output control unit 141 returns to the no-valid request state ST11 after a certain time has passed since the transition to the valid-requested state ST12, and the output value of the control unit 141 (the output value of the bus clock control signal) ) Is again set to a value (logic "1") indicating no bus clock valid request.

  FIG. 7 shows a state where the bus clock BCLK output operation is valid (bus clock output valid), the IO processor 12 of the IO processing device 10 is stopped, and the bus 20 has not been used for a certain period of time. 6 is a timing chart for explaining an operation when detected by a clock generation output control unit 31;

  Now, the clock generation output control unit 31 is in the valid output state ST1 in FIG. 2, and the bus clock control signal output control unit 141 of the IO processing device 10 is in the first no valid request state ST11 in FIG. To do. In this state, it is assumed that the IO processor 12 is stopped and the stop state signal 120 output from the IO processor 12 transits from logic “0” to logic “1”.

  In this state, it is assumed that the clock generation output control unit 31 detects a state where the bus 20 has not been used for a predetermined time (a bus transaction is in an idle state) at time t2 shown in FIG. Then, the clock generation output control unit 31 transitions to the invalid notice state ST2 as shown in FIG. In this state, unlike the case of the timing chart of FIG. 6, the IO processor 12 is in a stopped state, and therefore the operation described below is executed by the clock generation output control unit 31 and the bus clock control signal output control unit 141. The

  First, when the clock generation output control unit 31 transits to the invalid notice state ST2, the output value of the control unit 31 is switched from logic “0” to logic “1” for invalid notice (bus clock invalid notice). Then, the value of the bus clock control signal on the bus clock control signal line 21 (the value of the wired OR result) is switched from logic “0” to logic “1”.

  The bus clock control signal output control unit 141 receives the value of the bus clock control signal on the bus clock control signal line 21 (the value of the wired OR result), so that the clock generation output control unit 31 is notified of the invalid notice. Detect that. At this time, the bus clock control signal output control unit 141 is in the second state in the no-valid request state ST11. The IO processor 12 is stopped (the stop state signal 120 is logic “1”), and the activation request signal 140 is logic “0” indicating that there is no activation request.

  When the bus clock control signal output control unit 141 detects the invalid notice in such a state, the IO processor 12 is stopped and the activation request signal 140 indicates no activation request. Therefore, the state transits to the second no valid request state ST13. In the second no valid request state ST13, the bus clock control signal output control unit 141 sets the output value of the control unit 141 (the output value of the bus clock control signal) to a value (logic “1”) indicating no valid request. maintain. Then, the bus clock control signal output control unit 141 returns to the first no-valid request state ST11 when a predetermined time has elapsed since the transition to the second no-valid request state ST13.

  On the other hand, the clock generation output control unit 31 indicates that the value of the bus clock control signal (wired OR result) input from the bus clock control signal line 21 is logic “1” even after a predetermined time has elapsed from the invalid notice time t2. In the case of “,” it is determined that there is no valid request from the bus clock control signal output control unit 141. In other words, the bus clock control signal output control unit 141 determines that there is no valid request from the bus clock control signal output control unit 141 when only no valid request is input for a certain time from the invalid notice point t2. In this case, the clock generation output control unit 31 transits to the invalid output state ST3 for power saving. Here, it is assumed that the state transits to the invalid output state ST3 at time t3.

  In the invalid output state ST3, the clock generation output control unit 31 maintains the output value of the control unit 31 at the logic “1”, that is, the bus clock control signal (wired OR result on the bus clock control signal line 21). The operation of outputting the bus clock BCLK is stopped while the value is maintained at the logic “1”. Thereby, power saving of the computer system of FIG. 1 is achieved. At this time, the bus clock signal on the bus clock control signal line 21 indicates that the output operation of the bus clock BCLK by the clock generation output control unit 31 is invalid.

  The processor clock control unit 13 of the IO processing device 10 stops the operation when the output operation of the bus clock BCLK by the clock generation output control unit 31 becomes invalid (stopped). As a result, the generation of the processor clock 130 is stopped. The bus clock control signal output control unit 141 maintains the output value of the control unit 141 in a state where there is no valid request.

  FIG. 8 starts with a case where the clock generation output control unit 31 of the host system 30 detects that the bus 20 has not been used for a certain period of time when the activation request signal 140 indicates that there is a activation request. It is a timing chart for explaining operation.

  Now, the clock generation output control unit 31 is in the invalid output state ST3 in FIG. 2, and the bus clock control signal output control unit 141 is in the third state in the first no valid request state ST11 in FIG. To do. In the invalid output state ST3, as described above, the output operation of the bus clock BCLK by the clock generation output control unit 31 is invalid. Further, it is assumed that the IO processor 12 is stopped and the stop state signal 120 is logic “1”.

  In such a state, it is assumed that a request to use the bus 20 in the host system 30 (bus use start request) has occurred. When the clock generation output control unit 31 detects a bus use start request in the host system 30 in the invalid output state ST3, the clock generation output control unit 31 transits to the valid output state ST1. Then, the clock generation output control unit 31 performs an output operation of the bus clock BCLK in order to make the bus 20 usable. The clock generation output control unit 31 sets the output value of the control unit to logic “0” to indicate that the output operation of the bus clock BCLK is valid. As a result, the logical value of the bus clock control signal on the bus clock control signal line 21 (the value of the wired OR result) becomes logical “0”. In this state, the host system 30 can use the bus 20. On the other hand, the bus clock control signal output control unit 141 switches from the third state in the first valid request-free state ST11 to the second state in the state ST11.

  Therefore, the host system 30 accesses the control register 143 included in the clock / processor control unit 14 of the I / O processing device 10 via the bus 20, and logic “1” (second value) indicating that there is a start request in the register 143. ) 1-bit activation request control information is set. Then, a start request signal 140 having a logic “1” indicating that there is a start request is output from the control register 143. Note that a decoder that decodes the set value of the control register 143 may be provided so that the activation request signal 140 indicating that there is an activation request or no activation request is output by the data. In this case, the activation request signal output means is constituted by the control register 143 and the decoder.

  Now, it is assumed that the bus 20 is not used even after a lapse of a certain time after the bus 20 is used for accessing the control register 143 by the host system 30. As a result, it is assumed that the clock generation output control unit 31 detects a state where the bus 20 has not been used for a certain time in the effective output state ST1 at time t4 shown in FIG. Then, the clock generation output control unit 31 transits to the invalid notice state ST2.

  When the transition to the invalid notice state ST2 is made, the clock generation output control unit 31 switches the output value of the control unit 31 from logic “0” to logic “1” for invalid notice (bus clock invalid notice). Then, the value of the bus clock control signal on the bus clock control signal line 21 (the value of the wired OR result) is switched from logic “0” to logic “1”.

  The bus clock control signal output control unit 141 receives the value of the bus clock control signal on the bus clock control signal line 21 (the value of the wired OR result), so that the clock generation output control unit 31 is notified of the invalid notice. Detect that. At this time, the bus clock control signal output control unit 141 is in the second state in the no-valid request state ST11. Correspondence setting information indicating that the correspondence is valid is set in the setting register 142, and the activation request signal 140 indicates that activation is requested.

  The bus clock control signal output control unit 141 for which “correspondence valid” is designated by the correspondence setting information set in the setting register 142 is invalid in the state where there is no valid request ST11 and the activation request signal 140 indicates that there is a activation request. When the advance notice is detected, the process transits to a valid request state ST12. Then, the bus clock control signal output control unit 141 sets the output value of the control unit 141 to a value (logic “0”) indicating that there is a bus clock valid request. As a result, the value of the bus clock control signal on the bus clock control signal line 21 (the value of the wired OR result) becomes logic “0” indicating that there is a valid request.

  When the clock generation output control unit 31 inputs a bus clock control signal of logic “0” indicating that there is a valid request within a certain time from the notification point of invalidity notice, the clock generation output control unit 31 returns to the valid output state ST1. Then, the clock generation output control unit 31 sets the output value of the control unit 31 to a value (logic “0”) indicating that the bus clock is valid again while continuing the output operation of the bus clock BCLK.

  On the other hand, the bus clock control signal output control unit 141 returns to the no-valid request state ST11 after a certain period of time has elapsed since the transition to the valid-requested state ST12. Then, the bus clock control signal output control unit 141 sets the output value of the control unit 141 to a value (logic “1”) indicating that there is no valid request again.

  Now, in the valid output state ST1, it is assumed that the host system 30 accesses the control register 143 and sets 1-bit activation request control information of logic “0” indicating no activation request in the register 143. Then, the activation request signal 140 of logic “0” indicating that there is no activation request is output from the control register 143. Thereafter, when the bus 20 is not used for a certain period of time, the clock generation output control unit 31 transitions to the invalid notice state ST2. Then, the clock generation output control unit 31 notifies the bus clock control signal output control unit 141 of the invalid notice. At this time, the IO processor 12 is assumed to be operating. When the clock generation output control unit 31 is notified of the invalid notice, the bus clock control signal output control unit 141 indicates that the activation request signal 140 indicates no activation request, and the IO processor 12 is operating. Transition to the presence state ST12.

  In the above embodiment, one IO processing device 10 is connected to the host system 30 by the bus 20. However, a plurality of IO processing devices having the same configuration as the IO processing device 10 may be connected to the host system 30 via the bus 20.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment.

1 is a block diagram showing a configuration of a computer system including an IO processing device according to an embodiment of the present invention. The state transition diagram for demonstrating the detail of the function of the clock generation output control part 31 in FIG. The output value of the clock generation output control unit 31, the output value of the bus clock control signal output control unit 141, the logical value of the bus clock control signal on the bus clock control signal line 21, and the state of the bus clock BCLK (bus clock output state) FIG. 6 is a diagram illustrating a correspondence relationship between the clock generation output control unit 31 and the state. The state transition diagram for demonstrating the detail of the function of the bus clock control signal output control part 141 in FIG. When the bus clock control signal output control unit 141 receives an invalid notice from the clock generation output control unit 31, the setting value of the setting register 142, the setting value of the control register 143, the input value of the stop state signal 120, and the bus The figure which shows the correspondence with the state (output value of a bus clock control signal) of the clock control signal output control part 141. To describe an operation when a state in which the bus 20 is not used for a predetermined time while the output operation of the bus clock BCLK is valid and the IO processor 12 of the IO processing device 10 is operating is detected. Timing chart To describe the operation when a state in which the bus 20 is not used for a certain period of time while the output operation of the bus clock BCLK is valid and the IO processor 12 of the IO processing device 10 is stopped is detected. Timing chart. 7 is a timing chart for explaining an operation including a case where a state in which the bus 20 is not used for a certain period of time is detected in a state in which the activation request signal 140 indicates that there is an activation request.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... IO processing unit, 11 ... IO control part, 12 ... IO processor, 13 ... Processor clock control part 1, 14 ... Clock / processor control part, 20 ... Bus, 21 ... Bus clock control signal line, 30 ... Host system, DESCRIPTION OF SYMBOLS 31 ... Clock generation output control part, 40 ... IO device, 120 ... Stop state signal, 140 ... Startup request signal, 141 ... Bus clock control signal output control part (bus clock control request means), 142 ... Setting register, 143 ... Control register.

Claims (10)

In the input / output processing apparatus that is connected to the host system via a bus that operates on a bus clock output by the clock generation output control means of the host system and performs input / output processing between the input / output device and the host system,
Input / output control means for performing input / output between the input / output device and the bus;
An input / output processor that operates according to a processor clock and operates the input / output control means by an instruction execution operation according to a program, and indicates that when the instruction execution operation is stopped, the input / output processor is stopped. An input / output processor that outputs a state signal and resumes the instruction execution operation to deactivate the stop state signal when the start is requested by an active start request signal in the stop state;
Processor clock control means for inputting the bus clock, generating the processor clock based on the bus clock, and outputting the processor clock to the input / output processor, wherein the active stop state signal is output by the input / output processor. Is output, and the processor clock that resumes the output of the processor clock to the input / output processor when the activation is requested by the activation request signal in the processor clock output halt state. Control means;
Bus clock control request means for requesting an effective output state in which the bus clock output operation by the clock generation output control means is valid according to the states of the input / output processor and the clock generation output control means,
The bus clock control request means includes
The bus output by the clock generation output control means as a result of detecting that the bus generation output control means in the valid output state in which the bus clock output operation is in effect is not used for a predetermined time. An invalid notice detection means for detecting an invalid notice for notifying that the clock output operation is invalid;
When the invalid notice is detected, if the activation is requested by the activation request signal or the inactive stop state signal is output by the input / output processor, the clock generation output is output within a predetermined time. An input / output processing apparatus comprising: effective request response means for requesting the control means to continue the effective output state.   Even when the invalid request notice is detected, if the activation request response means is not requested for activation by the activation request signal and the input / output processor outputs the active stop state signal, 2. The input / output processing apparatus according to claim 1, wherein the clock generation output control unit is inhibited from requesting the continuation of the effective output state.   2. The input / output processing apparatus according to claim 1, further comprising start request signal output means for outputting the active start request signal in response to a specific access through the bus by the host system.   The activation request signal output means includes a control register in which activation request control information indicating an activation request is set by the specific access by the host system, and the activation request based on the activation request control information set in the register 4. The input / output processing apparatus according to claim 3, wherein the input / output processing apparatus outputs a signal. Further comprising a setting register for setting correspondence setting information for designating whether to correspond to the invalid notice by access via the bus by the host system;
The valid request response means requests the clock generation output control means to continue the valid output state when the correspondence setting information set in the setting register specifies that the invalid notice is not supported. The input / output processing device according to claim 1, wherein the input / output processing device is always inhibited. The bus clock control request means is a bus clock control signal line used for transferring a bus clock control signal that can be input / output by both the bus clock control request means and the clock generation output control means, and The clock generation output control is performed via the bus clock control signal line to which the inactive bus clock control signal is transferred only when both the request unit and the clock generation output control unit output the inactive bus clock control signal. Connected with the means,
The invalid notice detection unit is configured such that the bus clock control signal input from the bus clock control signal line by the bus clock control request unit is switched from an active state to an inactive state by the clock generation output control unit. Detected an invalid notice,
The valid request response means requests the clock generation output control means to continue the valid output state by outputting an active bus clock control signal to the bus clock control signal line. The input / output processing apparatus according to 2.   The valid request response means suppresses requesting the clock generation output control means to continue the valid output state by outputting an inactive bus clock control signal to the bus clock control signal line, 7. The input / output processing apparatus according to claim 6, wherein the clock generation output control means is notified that continuation of the valid output state is not required. A bus that operates on a bus clock;
A host system using an input / output device via the bus, the host system including clock generation output control means for executing an output operation for generating and outputting the bus clock;
An input / output processing device connected to the host system via the bus and performing input / output processing between the input / output device and the host system;
The input / output processing device includes:
Input / output control means for performing input / output between the input / output device and the bus;
An input / output processor that operates according to a processor clock and operates the input / output control means by an instruction execution operation according to a program, and indicates that when the instruction execution operation is stopped, the input / output processor is stopped. An input / output processor that outputs a state signal and resumes the instruction execution operation to deactivate the stop state signal when the start is requested by an active start request signal in the stop state;
Processor clock control means for inputting the bus clock, generating the processor clock based on the bus clock, and outputting the processor clock to the input / output processor, wherein the active stop state signal is output by the input / output processor. Is output, and the processor clock that resumes the output of the processor clock to the input / output processor when the activation is requested by the activation request signal in the processor clock output halt state. Control means;
Bus clock control request means for requesting an effective output state in which the bus clock output operation by the clock generation output control means is valid according to the states of the input / output processor and the clock generation output control means,
The clock generation output control means includes:
A bus non-use state detecting means for detecting a bus non-use state in which the bus is not used for a predetermined time when the output operation of the bus clock is in a valid output state;
An invalid notice means for notifying the bus clock control request means of an invalid notice for notifying that the output operation of the bus clock is invalidated in response to detection of the bus non-use state,
The bus clock control request means includes
An invalid notice detection means for detecting the invalid notice;
When the invalid notice is detected, if the activation is requested by the activation request signal or the inactive stop state signal is output by the input / output processor, the clock generation output is output within a predetermined time. And a valid request response means for requesting the control means to continue the valid output state.   The clock generation output control means includes valid request detection means for detecting that the continuation of the valid output state is requested within a predetermined time from the invalid notice time by the invalid notice means, and the valid output within the certain time. When the continuation of the state is requested, the effective output state is continued, and when the continuation of the valid output state is not requested within the predetermined time, the bus clock output operation is stopped, and the bus 9. The computer system according to claim 8, wherein the clock output operation transits to an invalid invalid output state. The clock generation output control means includes:
Bus use start detecting means for detecting a bus use start request for starting use of the bus generated in the host system;
Valid output notifying means for resuming the output operation of the bus clock and notifying the bus clock control requesting means that it is in the valid output state when the bus use start request is detected in the invalid output state; The computer system according to claim 9, comprising:

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