TW594466B - Power management method for microprocessor - Google Patents

Abstract

The present invention provides a power management method for microprocessor, which is applied in a computer platform with the microprocessor and the system control chipset supporting the advanced power management (APM). The method uses a software to control the system control chipset when the microprocessor is at the idle state, and drives the microprocessor into a sleeping mode, and further controls the microprocessor to cut off the system bus to achieve the effect of effectively saving the power consumption and reducing the temperature.

Description

594466 A7 B7 V. Description of the Invention-) [Field of the Invention] The present invention relates to a power management method, in particular to a power management method of a microprocessor in which software and firmware are parallelized in a computer platform. 5 [Know-how] The rise of the concept of power management is closely related to the development of notebook computers. 'Because of the poor battery manufacturing technology of the most important power source of early notebook computers, the amount of stored power is limited, so how to save power to extend notes Model computer use time has become the focus of manufacturers' research and development. Therefore, in 1 gg and 2 years, INTEL and Microsoft proposed Advanced Power Management (APM) so that when the computer was not operated for a period of time, the basic input / output system (Basic Input / Output System (BIOS) to turn off power to peripheral devices (such as hard disks, monitors, keyboards, and mice) and put the microprocessor into a power-saving mode (that is, in a low-power state) to reduce power consumption. . This advanced power management interface was first implemented by notebook computers and finally extended to desktop computers. In the advanced power management interface, the command set for controlling peripheral devices and microprocessors for power control and management is stored in the basic input and output system, and then when power control is desired, the basic input and output system is called or the operation department, Call basic input output system. Therefore, the advanced power management interface is mainly responsible for the basic input and output system. In addition, as the X operation frequency of the micro-processing H is getting higher and higher, the operating temperature will also increase accordingly ', forming a high temperature that the microprocessor may burn. At this time, such as 10 15 20

(Please read the precautions on the back before filling out this page)-»-， 可 — V. Description of the invention g) How to make the microprocessor operate at high temperature The cooling fan also has a major focus. At present, in addition to matching the device when the temperature is too high. Timely π 2 reading software to control the micro-processing drop. Due to the power consumption and dissipation rate of the electronic components, it is possible to reduce the power consumption of the electronic components to reduce the heat generated by the electronic components. According to this, the cooling system is based on 10 15 20 (please read the precautions on the back before filling in this page). Enter "two 1" on the surface to sigh leaves, mainly when the temperature is too high, the basic transmission system detection When this is abnormal, the cooling instruction mn will be sent to the micro-level, and once the microprocessor receives this cooling instruction, it will enter the power saving mode, which will break it into a low power state and achieve the cooling effect. However, because the advanced power management interface transfers all power management to the system, its defined functions are more limited, and it can only achieve «something like a display, hard disk, microprocessor, etc. ) After a few readings, it enters the power saving mode and performs simple monitoring. The power saving is not the most n. After the actual boot, the entire computer is actually dominated and controlled by the operating system's actual contact with the peripheral device's scheduling, so the manufacturers believe that the power supply The operating center to be managed should be transferred from the basic input output system to the operating system to achieve the highest power management efficiency. Therefore, a new generation of power / configuration control interface was released in 1999, which is the advanced architecture power control interface (Advanced Configuration and Power Interface (AGPI). And the advanced architecture power control interface is equivalent to a set of extremely complex new control language / interface protocols, enabling new devices and operating systems to understand the new communication mode, and defining four to five for various peripheral components. This kind of power switching mode is redundantly different from the previous advanced power management interface Vendors need to adjust and change the design of various computer components to comply with the advanced architecture power control interface. Page 5 This paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 366 594466 A7 I— ________ ^ _ V. Invention Note g) and the integration of parts with each other has become the focus of current manufacturers' efforts. As for the microprocessor, its power saving mode increases according to different degrees of power saving, such as the rest (Ha It) mode (C1), sleep (stop) Grant) mode (C2) and deep sleep mode (C3), while the previous power saving interface of the advanced power management interface is only 5 疋 equivalent to the rest mode (C1), so there is still room for improvement in the cooling software that only controls the microprocessor to the rest mode Moreover, due to the change of the power management operation interface, the cooling software designed for the advanced power management interface may no longer be suitable for the advanced architecture power control interface. At present, many manufacturers have launched 10 products 1 ^ that comply with the advanced architecture power control interface, so How to integrate the hardware architectures of these different manufacturers for power management Furthermore, because the execution efficiency of the microprocessor has been greatly improved, most of its time (for example, more than 90% of the time) is in the idle state (that is, the state without data processing). Microprocessor interposition 15㈣: Putting it into power-saving mode can not only save power but also reduce the temperature of the microprocessor. There are also softwares on the market that control this, which is output when the microprocessor is idle. " "HLT" instruction puts it into a power-saving state, so that the temperature of the microprocessor can be reduced (for example, 5 to 10 degrees). However, because this software is a direct output, HLT ,, instruction, it can only make the microprocessor enter Humou Model 20 < while still unable to operate the microprocessor into deeper power saving modes (❹, C2, C3), there is still room for improvement in power saving and cooling effects. Therefore, if the microprocessor can be put into a deeper power saving mode (such as the sleep mode), the temperature of the microprocessor can be further reduced and the power consumption can be saved. ㉟According to the advanced architecture power control interface ’In the power saving mode, the microprocessor L _ _ page 6 This paper size is turned over) A4 specification (210X297 mm) " ------

1! ^^ ---- (Please read the precautions on the back before filling this page), Yiding | 367 V. Description of the invention) The mode that can quickly perform signal processing when there is an interrupt signal input is rest Mode (C1) and sleep mode (C2). Therefore, the inventor of this case considers that if the microprocessor can be put into sleep mode in the interposed state, it will be more effective in controlling power consumption and cooling. However, the advanced architecture power control 5 interface is no longer used as a basic input and output system. Power supply control, so it can't be controlled in the way that the software operates the basic I / O system, but find other ways to control. [Summary of the Invention] Therefore, an object of the present invention is to provide a power management method for a microprocessor that can further save power consumption. Another object of the present invention is to provide a power management method for a microprocessor that can more effectively reduce the temperature of a microprocessor. Therefore, a microprocessor power management method of the present invention is controlled by a user and executed in a computer platform. The computer platform includes a computer 15 host and a display, and the computer host has a motherboard and a The microprocessor 'on the motherboard' and the motherboard has a system control chipset 'is responsible for the interconnection and communication of the components in the computer platform. The method includes the following steps: A) determine whether the components of the computer platform meet Advanced architecture power interface 20 faces; B) If yes, 'determine whether the microprocessor is in an idle state bear; and ... C) If the microprocessor is in the idle state, make the system control chipset make the microprocessor Enter a sleep mode, so that one of the microprocessors is ______ page 7 This paper size applies to Chinese National Standard (CNS) A4 specifications (210X297 mm) 594466 A7 __ B7 V. Description of the invention The bank is no longer connected to the system control chip and reduces the power supply to the microprocessor. [Simplified description of the drawings] Other features and advantages of the present invention will be clearly understood in the following detailed description of the preferred embodiment with reference to the drawings. In the drawings: The first picture is a motherboard Schematic diagram of the architecture. The second figure is a block diagram of a preferred embodiment of the present invention. The third diagram is a schematic diagram of a computer platform implementing a preferred embodiment of the present invention. 10 The fourth diagram is a flowchart of a preferred embodiment of the present invention. The fifth figure is an example of a user input interface displayed in a window in a preferred embodiment of the present invention. [Detailed description of the preferred embodiment] Since the present invention is matched with the existing hardware architecture to control the electrical source management of the microprocessor, the following first introduces the hardware architecture of the microprocessor and related components in order to facilitate This case is easier to understand. As shown in the first figure, a combination diagram of a motherboard and a microprocessor 2 is shown. The microprocessor 2 can be regarded as the center of the entire computer, and most tasks, interrupt processing or events need to be processed or processed by the microprocessor 2 20 in order to transfer correct data or signals to each other. In addition to the microprocessor 2, the core components of the computer are motherboards. The main purpose of the motherboard 1 is to serve as a connection and transmission medium between various hardware components and peripheral devices, including a micro-processing socket for inserting the microprocessor 2, a basic input and output system, and a memory for inserting. u memory __. _ page 8 This paper size is applicable ^ 3 National Standard (CNS) A4 size (210X297 mm) ^ (Please read the precautions on the back before filling this page) Order — 594466 A7 --- --- B7_ V. Description of the invention 翕) Slot and peripheral component connection interface (peripherai Component

Interconnect ’PCI) bus 12, memory bus 13, and other expansion slots and buses. In order to be able to control all peripheral components connected to the motherboard 1, the motherboard 1 is provided with a system control chipset 10. This system is a system control chipset 10 which has different functions according to the motherboard architecture. However, the common system control chipset 10 includes a North Bridge chip 101 and a South Bridge chip S02, the former is responsible for the display of the memory and Accelerated Graphics port (AGp) interface. Unit (also known as graphics card or display chip) 14, communication between memory u and micro 10 processor 2, which is responsible for PCI peripherals, hard disks, floppy disks, mice, keyboards and other devices. Here, for convenience Knowing the operating conditions such as temperature in the microprocessor 2, a temperature monitor 15 is also provided. The microprocessor 2 communicates with the North Bridge Crystal # 101 by its system bus 21, and the South Bridge chip 102 and the North Bridge chip ιοί and the microprocessor 2 and the 15 north bridge chip 101 and the microprocessor 2 respectively form signal lines 16, 17, 18 for transmitting control instructions. Because the main purpose of the present invention is to allow the microprocessor 2 to enter when it is idle. Hibernation mode, so the microprocessor 2 itself must have a hibernation mode, that is, it must comply with advanced architecture power interface standards, such as AMD microprocessors. Furthermore, in the past, the basic input and output system is used. The microprocessor was ordered to enter the sleep mode, so the inventor of the present case considered the use of other components to send more powerful power management functions, and found that there is a microprocessor in the system control chipset 10 that conforms to the advanced architecture power interface standard The mechanism for the device 2 to enter the sleep mode, such as the system control chipset of VIA or Shi Xitong. However, because of the paper A4 specification ⑵0X modest on page Θ) --- s (Please read the precautions on the back before filling this page )

594466 A7 V. Description of the invention 10 15 20 The microprocessor 2 and the system control chipset 10 are manufactured by different manufacturers, so that the software function must be coordinated and integrated before it can be applied, and the method of the present invention is triggered. The system controls the chipset 丨 0 to control the microprocessor 2 power management. The method of the present invention is a microprocessor power management program built into the computer platform 3 as shown in the second figure and can be executed under the operating system. The computer platform 3 may be a desktop computer, a notebook computer, or a palmtop computer. In this embodiment, a desktop computer is used as an example. The computer platform 3 includes a computer host 31, a display 32, Storage media (not shown) such as a disc, a keyboard 33 and a mouse 34, and so on. The computer main body 31 is provided with the motherboard 1 ′ as shown in the first figure and as shown in the third figure, at least one operating system 351 is stored in the storage medium 35, such as Windows 95/98 / ME designed for a personal computer or designed for a network environment. Windows NT / 2000, etc., and the microprocessor power management program 352 of this example. In the following, the execution process of this embodiment will be described in detail with reference to the third and fourth figures. First, at step 51, when the computer is booted and loaded into the operating system 351, the microprocessor power management program 352 is preset to be executed. Secondly, since the microprocessor power management program 352 needs to be enabled for execution in accordance with the microprocessor 2 that conforms to the power source of the advanced configuration, in step 52, it is determined whether the microprocessor 2 meets the requirements of the advanced architecture power interface. In this example, the microprocessor power management program 352 is the manufacturer and model of the microprocessor that conforms to the advanced architecture power interface standard. For example, AMD. In step 52, the microprocessor in the computer host 31 is compared. The manufacturer of 2 is consistent with " 疋 No /, any of the built-in data, and you can know that the microprocessor is _page 10 This paper is standard and the standard is turned off _ A4 specification (210X297 mm) (Please read the back first (Notes to fill out this page)

371. 594466 V. Description of the invention &) 10 15 20 Whether it meets the requirements. If it is judged in step 52 that the microprocessor 2 meets the requirements, then step 53 is continued; otherwise, if the requirements are not met, the program ends. • Because the operating system is designed for personal computers, such as Wudows9595 / 98 / ME or Windows nt / 2o00 for network environments, there may be differences in the driver program of the microprocessor power management program 352. Corresponds to adjustment changes, so the program in this example contains a set of driver designed to match the operating system of a personal computer and a driver designed for an operating system designed for a network environment to operate under different operating systems. Since most computers use the operating system of a personal computer, in this example, the microprocessor power management program 352 executes the driver of the operating system of the personal computer by default. In step 53, the type of the operating system is determined first. Whether it is an operating system for a personal computer, and if yes, proceed to step 56. On the contrary, if it is judged as negative in step 53, it means that the operating system of computer platform 3 should be designed for the gQ network environment, then go to step 54 and load another set of drivers that cooperate with this operating system to replace the original reservation Driver. Then, in step 55, it is judged whether the loading of another set of drivers is successful or not, and the process is terminated in a closed manner. If successful, the step% is edited. In step 56, it is determined whether the system control chipset 10 meets the requirements, that is, it is determined whether the system control chipset 1G complies with the advanced architecture power interface. If it is, then step 57 is continued, and if it is not, the process ends. In this example, the program and the model 352 of the system control chipset that conforms to the advanced architecture power interface standard are also used to compare the system control in the computer host 31 in the example of VIA or Shi Xitong. The cheap quotient of chipset iQ ^

Stomach 11 pages This paper size Lai Jin Guan Jiaqun (⑽A4 size (2: 297 mm T

Order 丨 (Please read the notes on the back before filling out this page)-# V. Description of the invention Whether the model and any of the built-in data are supported by the film group 10. If it matches, you can know that the system control crystal = control the south and north bridge crystals in the chipset 10, and you need to issue instructions by county or change the setting to enable the microprocessor 5 and follow the microprocessor manufacturer #sleep mode. In the sedan & mountain caused the system control chip group 7 to have "the control instruction address and content are all different. However, the North Bridge chip outputs a disconnection command and it hurts. Eight South Bridge Japan and Japan film 102 outputs a rest." The microprocessor 2 is put into the sleep mode, and the microprocessor 2 enters the sleep mode only when two conditions are met. Therefore, in step 10, the microprocessor power management program first sets the North Bridge; 4 1ni Di i 8 "Zhan Qiao 3 Diao Qiao Japanese film 101 drives its output to break each other :: to the microprocessor 2. Due to the manufacture of different manufacturers The microprocessor 2 " 2 controls the output instruction of the circuit breaker between the chipset 1G, but there is a difference. However, one bit of metadata in the matching Northbridge chip 101 is the microprocessor 15 20 == disconnect (disc_ect). This bit data is-check accuracy or a high level, and-start (such as the computer is turned on, restarted; or microprocessor 2 is not in sleep mode, etc.), this bit data is _ preset level (Such as low level or high level), 'and when the microprocessor 2 receives a sleep instruction and says that this bit data has been detected is not a preset level (for example, it has been changed from a bias to a high level or has been changed from a high level) To the low level), the 7-bus system bus 2 will be used. Therefore, this step 57 is to change the North Bridge chip 101 to the bit level used to cut the system bus 21. For the solution, Here is an example to illustrate, suppose the microprocessor 2 is a microprocessor and system control following 〇ηΚ, The chipset is VIA Π266A chipset, and when the bridge bridge chip 101 is VT8366A, there is a bit address 594466 A7 in the Northbridge chip m. 5. Description of the invention; (〇)-! — Is partial S2K timing control register of shift position 92 (this register is one ::: register 'data from 0 ~ 7), and the seventh bit in this register is defined as the standby sleep instruction to be tested The cut-off is activated at the time of exit, that is, the data level of the seventh bit and the system 5 bus 21 related to whether the microprocessor 2 cuts off the connection with the north bridge chip m, and the data of this bit is usually a low level ( 〇), and want to enter the sleep mode is the high level ⑴ 'so this step 57 in this example only needs to set the seventh bit in the register at offset position 92 in the Northbridge chip 101 as the high bit ^ as the disconnection instruction, The setting of the Northbridge chip 101 can be completed, and step 58 is continued. When step 57 is completed, because the microprocessor 2 still needs to detect the disconnection command and the sleep command at the same time, it will enter the sleep mode. Therefore, at this time, Microprocessor H 2 still does not enter sleep mode and system bus 2 is not turned off-in step 58 The microprocessor power management program 352 will continuously monitor whether the microprocessor 2 is in an idle state, that is, it does not have any signal or instruction input 15 inputs, and when it is judged that the microprocessor 2 is in an idle state, skip to step 59; otherwise, When it is not determined that the microprocessor 2 is in an interposed state, skip to step 63. At present, the operating frequency of the microprocessor 2 is high, such as 800 MHz, 1.2 GHz, 2 GHz, etc., so that it is located in an interposed state. The probability of the state is getting higher and higher. According to statistics, 90% of the microprocessors operating at frequencies above 500MHz are in the intervening state. When the microprocessor 2 is in the intervening state, there is no signal. Or the instruction is input, but the microprocessor 2 still executes the empty data at the original speed, which causes the load of the microprocessor 2 to remain high and the working temperature cannot be effectively reduced. In step 59, the microprocessor power management program 352 is judged to be small. Page 13 This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling in this page) May 374 594466 A7 ---- B7_____ V. Description of the invention il) When the processor 2 is really in an idle state, the south bridge chip 102 is caused to dig out the internal sleep instruction and output it to the microprocessor 2. Due to the difference between the manufacturer of the south bridge chip ι02 and the microprocessor 2, the storage address of the hibernation instruction in the south bridge chip 102 may be different or the content is not the same. South bridge crystal chip and the microprocessor 5 internal settings The mutual cooperation causes the microprocessor 2 to enter the sleep mode as soon as it receives the sleep command output from the south bridge chip 102. In order to make this embodiment easier to understand, here is an example. Assume that the microprocessor 2 is the microprocessor and system control chipset of AMD Athlon K7, the VIA KT266A chipset, and the south bridge chip 102. It is VT8233, the microprocessor 2 10 series is preset to receive the sleep command STPCLK #, and it will start to enter the sleep mode (at this time, the case where the Northbridge chip 101 has output a disconnection command), and the Southbridge chip 102- The content of the data within 14 addresses of the input increment offset (I / O Offset) in the microprocessor power management register defines the microprocessor's second level (Processor Level 2), which is the sleep instruction STpCLK #. 15 In step 59, the microprocessor power management program disconnects the south bridge chip 102 to read the data valley of the input / output offset 14 in the microprocessor power management register, and then uses this data as the sleep instruction. STpcLK # is continuously output to the microprocessor 2. Immediately after the microprocessor 2 receives the sleep instruction STpcLK #, it enters step 60. In step 60, it means that the microprocessor 2 has received the sleep instruction and disconnected. Instruction, the microprocessor 2 will Enter the sleep mode, cut off the system bus 21 and latch the information on it according to the circuit-breaking instruction to pass when the connection is restored, and reset the working sequence to zero, so that the operating frequency is reduced to zero and the calculation or data processing is stopped. . In this way, compared with the rest mode in the prior art, page 14) 舛 466 A7 ------------- B7 V. Description of the invention) The present invention allows the microprocessor 2 to enter the sleep mode, except that In addition to stopping the microprocessor 2, it also cuts off the connection of the system bus 21, so that it can indeed obtain a more power-saving effect than the conventional one, and because the power consumption is reduced, the temperature of the microprocessor 2 is also reduced. Can be effectively reduced. 5 Next, in step 61, the microprocessor 2 determines whether the interrupt signal is input, such as INTR, smi, and SCI. If sometimes, it goes to step 62 to trigger the microprocessor 2 to wake up, otherwise continue to the step. 63. In step 62, when the microprocessor power management program 3 5 2 receives a message that the microprocessor 2 is fed with an interrupt signal, it will cause the south bridge chip 10 to no longer output a sleep command 10, so that the microprocessor 2 Leave the sleep mode and connect to the system bus 21 to work according to the interrupt signal content. This interrupt signal can be issued by any component or by the microprocessor 2 itself, and the contents of the tasking are different according to different requirements, such as requesting service or error report. In addition, the interrupt signal can be divided into two types: a hardware interrupt input by a user via a keyboard and a mouse, and a software interrupt such as the execution or shutdown of an application program. After step 62 ends, it will return to step 58. The microprocessor power management program 352 will continue to detect whether the microprocessor 2 is idle, and when the microprocessor 2 is idle again, the above steps 59 ° and 206 are performed. To put it into sleep mode to effectively save power consumption and reduce temperature. · At step 63, the microprocessor power management program 352 detects whether there is a shutdown command input. This shutdown command can be input by the user to end the execution of the microprocessor power management program 352, so when the microprocessor power management Process _______ Page 15 'Lai fiMCNS) Μ Examination (210X297 mm) " — 376 (Please read the precautions on the back before filling this page)

594466 A7 B7 V. Description of Invention ί 3 10 15 20 When the 352 receives the shutdown command, it will cancel the setting of North Bridge Chip 101 and South Bridge Chip 102 and end the execution of the program. Conversely, when the shutdown command input is not detected in step ⑽, skip back to step 61 to continue detecting whether there is an interrupt signal input. It is worth noting that step 63 in this process can be executed synchronously after the microprocessor power management program 352, that is, in steps 52 ~ 62, that is, once the command input is turned off during the execution, then End program execution. In this way, it is convenient for the user to close the execution of the program at any time that needs to be performed, such as when a large number of image files are to be processed, and the hard disk is reorganized, etc., and the shutdown command can be entered to end the program to avoid interfering with subsequent operations. In addition, the microprocessor power management program 352 of this embodiment is set to be automatically loaded and executed after the operating system 3 51 is started. For the convenience of the user, the microprocessor power management program 352 can be installed in the window of the display 32. A pattern is formed on the surface, and as shown in the fifth figure, the pattern 71 can be reduced in the task bar 72, and when the pattern 71 is moved by the user using an input device such as a keyboard 33 or a mouse 34, When pressed, the function list 73 'is displayed, and the function list 73 has a control button (Enable Cooler) 731, a disable control button (Disable Cooller) 732, an explanation control button (About) 733 and a Exit the control key (Quit) 734. The enable control key 731 causes the program to be executed when the user presses with the cursor, so that the microprocessor 2 enters the sleep mode in the idle state. The close control key 732 closes the execution of the program correspondingly when the user presses the cursor to close the application of this program. When the user presses the description control key 733 with the cursor, a description of the purpose of the microprocessor power management program 352 will pop up, and the report will be page 16 (please read the precautions on the back before filling in this page) • Order | This The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 594466 A7 _______B7_ V. Description of the invention ί4) When the user presses the leave control key 734 with the cursor, he leaves the menu 73 (even if taskbar 72 disappears in the window) To return to display by the small pattern 71 only. Thereby, the effect of facilitating user operation can be achieved. According to the foregoing, the program of the present invention does have the following advantages: 5 (1) Convenient to use: The present invention uses the hardware of the microprocessor 2 and the system control chipset 10 to write the program, and it is first screened to meet the requirements during execution. Hardware structure (such as steps 52, 56) to avoid the program running under the hardware structure that does not meet the requirements, causing invalid operation of the program, and even affecting the work efficiency of the computer platform 3. In this way, the judgment of the microprocessor 2 and the system control chipset 10 by using steps 52 and 56 allows the program to decide not to execute when the hardware environment does not comply, even if the user does not know whether the hardware conditions are met. Solve the problem caused by the user running in an environment not supported by the microprocessor power management program 352, and the microprocessor power management program 352 will also make appropriate changes for different operating systems in steps 15 53 ~ 55. In this way, the user does not need to read the operation manual that complies with the microprocessor power management program before the ladies program to know its operating environment and does not need to check whether the software or hardware manufacturer or serial number meets the conditions. The microprocessor power management program 352 It will automatically determine whether the hardware is compatible and replace the driver that complies with the operating system 352 of the computer platform 3 by itself, so as to achieve user-friendly installation and use ^. In addition, since the microprocessor power management program 352 provides a window interface (such as the fifth figure) for the user to operate, the convenience of the user operation can be increased. ⑵Power management is more efficient: + page 17 This paper size applies the Chinese National Standard (CNS) Α4 specification (2ι〇χ297 公 董)-

1. One-T—C, please read the notes on the back before filling in this page} W4466 ίο 15 20 、 Explanation of the invention: In the conventional technology, only the microprocessor enters the rest mode in the idle state. The invention makes the microcomputer The processor 2 enters the sleep mode when it is idle, so that the timing of the microprocessor 2 becomes zero and cuts off the system bus 21, and then causes the microprocessor 2 to stop data processing and signal transmission on the system bus 21. However, when there is an interrupt signal input, the microprocessor 2 is awakened without affecting the user operation, so as to achieve a better and effective reduction of power consumption without affecting the system performance. (3) The temperature of the microprocessor 2 is effectively reduced: Because the operating frequency of the microprocessor 2 is reset to zero and the connection of the system bus 21 is cut off, the load of the microprocessor 2 in the idle state is compared. It is less in the past, and the power consumption is reduced accordingly, so that the heat dissipated due to the operation of the microprocessor 2 in the interposed state is also effectively reduced, so that the temperature of the microprocessor 2 can be greatly reduced. At the same time, because the microprocessor 2 is kept in a drastically reduced temperature condition, the temperature of the microprocessor 2 can be maintained at a lower temperature, so that even if the workload of the microprocessor 2 suddenly increases and the temperature is greatly increased, After the increase, the temperature is less than the allowable temperature of the microprocessor 2, so that the life of the microprocessor 2 can also be effectively increased. However, the above are only the preferred embodiments of the present invention. It is not necessary to limit the scope of implementation of the present invention, that is, the simple equivalent changes made according to the patent application and the description of the present invention. And modifications should still fall within the scope of the invention patent. Page 18 3/9 f Ne Xian ((Let 297 mm) (Please read the precautions on the back before filling this page)

594466 A7 B7 V. Description of the invention 6) [Comparison of component numbers] 1 Mother board 1 0 1 Northbridge chip 11 Memory 1 3 Memory bus 1 5 Temperature monitor 2 Microprocessor 3 Computer platform 32 Display 34 Mouse 1 0 System control chipset 102 South bridge chip 12 PCI bus 1 4 Display unit 1 6, 1 7, 1 8 Signal line 21 System bus 31 Computer host 33 Keyboard 35 Storage media 351 Operating system 3 5 2 Microprocessor power management program 71 Pattern 72 work bar 73 function table 731 enable control key 732 close control key 733 description control key 734 leave instruction page 19 This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the note on the back first (Fill in this page again) 388

Claims (1)

Patent application scope 10 15 20 •: A microprocessor power management method is executed in a computer platform. The computer platform includes a computer host and a display: the electrical host has a motherboard and a motherboard.理 2 processor, and the motherboard has a system control chipset, which connects and communicates with the components in the computer platform, and the microprocessor and the system control chipset are in accordance with the advanced architecture power interface. It includes the following steps: A) determining whether the microprocessor is in an idle state; and B) if the microprocessor is in the idle state, causing the system to control the crystal set to put the microprocessor into a sleep mode so that the microprocessor Microcontroller's system bus is no longer connected to the system control chip and has low power supply to the microprocessor. 2. The method according to item 丨 in the scope of the patent application, wherein the control chip set has a north bridge chip and a south bridge chip, and in step B), the north bridge chip outputs a disconnection instruction and the south bridge crystal = continued Outputting a sleep command to the microprocessor 'causes the microprocessor to enter the sleep mode. 3. The method according to item 2 of the scope of patent application, further comprising: step C), if the microprocessor detects an interrupt signal input, the microprocessor processes the sleep mode * to resume the action and skips back to the step A) 〇4. The method as described in item 3 of the scope of patent application, wherein in step ii), the south bridge chip of the system control chipset stops outputting the sleep instruction when the interrupt number is input, so that the microcomputer The processor's declining order at the processor chip is in accordance with the Chinese National Standard (CNS) A4 specification (210X297 mm) 594466 A8 68 C8 D8. The scope of patent application is 15 20 this sleep mode. 5. The method described in item 1 of the scope of the patent application for printing further includes a step D) before the step A), so that the driver of the method is suitable for execution under the operating system of the computer platform. 6. The method according to item 丨 of the scope of patent application, wherein in step D), it is judged whether the operating system of the computer platform is a preset operating system that cooperates with a preset driver, and it is judged as When it does, the next steps are performed. 7. The method as described in item 6 of the scope of patent application, wherein, in step D), when it is determined that the operating system of the computer platform is not the preset operating system or system, Be, J replaces the preset driver Cooperate with the driver of the operating system. 8. The method described in item (i) of the scope of patent application, wherein, when step A) is performed, a window pattern is displayed on the display as a user input interface. 9. The method as described in item 8 of the Zhongji patent range, wherein, when the scheme is selected, a function table containing a plurality of control keys is displayed on the display. (2) The method according to item 9 of the scope of patent application, wherein the function table includes an enable control key, which causes the microprocessor to enter the sleep mode in the interposed state when the user starts. The method as described in item 9 of the scope of the patent application, wherein = means include-close control key ’means that when the user starts, the social microprocessing # enters the sleep mode in the set state. -, Tr_ ............ (Please read the notes on the back before filling out this page) 594466 A8 B8 C8 ________ D8_ VI. Application for Patent Scope. 1 2 · The method as described in item 9 of the scope of patent application, wherein the function table includes a description control key for displaying a description of the use of the program when the user starts it. 5 1 3 · The method as described in item 9 of the scope of patent application, wherein the function table includes a leave control key to make the 4 meter b meter no longer displayed when the user starts it. 14. · A microprocessor power management method is controlled by a user and executed in a computer platform. The computer platform includes a computer host and a display. The computer host has a motherboard and a motherboard. Microprocessor, and the motherboard has a system control chipset, which is responsible for the interconnection and communication of components in the computer platform. The method includes the following steps: A) determine whether the components of the computer platform meet the advanced architecture power supply interface 15); B) if yes, determine whether the microprocessor is in an idle state; and C) if the microprocessor is in the idle state, make the system control chip and the group put the microprocessor into a sleep mode In order to reconnect the system's chip with the 20Slf system at the micro level and reduce the power supply to the microprocessor. 15. As described in item 14 of the scope of patent application, which is / 2 :, wherein step A) includes the following steps: Α-υ judges whether the microprocessor meets the advanced architecture power interface; page 22__ 本Paper size applies + S National Standard (CNS) A4 specification (21GX297). ——————, (Please read the precautions on the back before filling this page). Order — 594466 A8 B8 C8 Order 594466 A8 B8 C8 VI. Application phase ~-~ B) ° 21. As described in the method of applying for the scope of the patent No. 20, in the step ㈨, the south bridge chip of the system control chip set is in the When the signal is input, stop outputting the sleep instruction to make the microprocessor 5 leave the sleep mode. 22. The method described in item 15 of the scope of patent application, further comprising a step after step A) and step E), forming a window pattern displayed on the display as a user input interface. 23. The method according to item 22 of the scope of patent application, wherein the pattern in step 10) of step E) is displayed on the display with a function table containing a plurality of control keys when selected by the user. 24. The method according to item 23 of the scope of patent application, wherein the function table in step E) includes a control key for consistent energy, and when the user starts, the microprocessor enters the microprocessor in the idle state. The rest 15 sleep mode. 25. The method according to item 23 of the scope of patent application, wherein the function table in step E) includes a close control key, and when the user starts, ends the microprocessor in the idle state. Enter the function of this sleep mode. 20 2 6 · The method as described in item 23 of the scope of patent application, wherein the function table in step E) contains a description control key for displaying the method when the user starts Intended use. 27. The method according to item 23 of the scope of patent application, wherein the function table in step E) includes a leave control key for applying the Chinese National Standard (CNS) A4 to the paper size on page 24 Specifications (210 X 297 mm) Φ: (Please read the precautions on the back before filling out this page). Order · 594466 A8 B8 C8 D8 When the user starts the patent application, the menu will no longer be displayed on page 5 2 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page)