JP4527097B2 - Network interface - Google Patents

Description

  The present invention relates to a network interface having at least one of a disconnect mode and a suspend mode in addition to an active mode.

  An IEEE 1394 bus system is standardized as a high-speed bus system. The IEEE 1394 bus system is a serial bus system and is mutually connected to IEEE 1394. An electronic device having an interface board (hereinafter simply referred to as an IEEE board) conforming to the standard a is connected by a standard cable (hereinafter simply referred to as IEEE cable) conforming to the IEEE 1394 standard. The IEEE cable employs a twisted pair cable including two pairs of two twisted wires through which differential signals flow.

  In addition to the active mode, the IEEE board defines a disconnect mode and a suspend mode. The active mode is a mode that is set when exchanging information such as packet data with an opposite node. The disconnect mode is a mode set when the opposing node is not connected. The suspend mode is a mode that is set when the opposing nodes are connected but packet data is not exchanged between the electronic devices connected to each other.

  The active mode and the suspend mode are set in the PHY chip of the IEEE board. The PHY chip is roughly composed of a cable I / F and a digital control unit that processes a signal output from the cable I / F.

  The cable I / F included in the IEEE board detects transmission / reception data, a connect detection signal that is asserted (Low) when the opposite node is connected, and Bias_ detection that is asserted (High) when packet data is exchanged. Various signals including the signal are output to the digital control unit.

  The digital control unit sets the disconnect mode, the suspend mode, and the active mode according to the values of the connect detection signal and the Bias_ detection signal. Specifically, the disconnect mode is set when the connect detection signal is in a negated state, and functions other than the function for executing the mode change process in response to the change in the connect detection signal are stopped.

  Also, the digital control unit sets the suspend mode when the Bias_detection signal remains in the negated state and the connect detection signal switches to the asserted state, and responds to changes in the connect detection signal and the Bias_detection signal. Stop functions other than the function that executes mode change processing. If the connect detection signal is switched to the negated state when the suspend mode is set, the disconnect mode is entered. On the other hand, when the Bias_detection signal is switched to the asserted state, the mode shifts to the active mode, and all functions other than the function for processing the connect detection signal are operated.

  IEEE 1394. The suspend mode provided in the interface board compliant with the standard a is to reduce the power consumed by each IEEE board when information such as packet data is not exchanged between electronic devices connected by the IEEE cable. Is the mode provided in

  However, even when the suspend mode is set, the clock signal generator in the IEEE board, particularly in the PHY chip, continues to operate. Inside the PHY chip, high-speed data processing at a maximum of 400 Mbps is performed. Correspondingly, the clock signal generation circuit generates a clock signal with a very high frequency, and the generation of the clock signal with a high frequency is accompanied by a large amount of power consumption.

  In order to save power, the clock signal generator may be stopped. However, if the clock signal generation unit is also stopped when the suspend mode is set, all signal processing functions in the PHY chip including processing of the connection detection signal detected in the cable I / F are stopped. For example, even when the electronic device is removed from the IEEE cable, the transition process from the suspend mode to the disconnect mode cannot be executed. In addition, there is a problem that even if information such as packet data is transmitted from the opposing electronic device, this cannot be detected and the mode cannot be shifted to the active mode. Note that the same problem occurs even when the clock signal generator is stopped when the disconnect mode is set.

  An object of the present invention is to provide a network interface which is an interface board typified by an IEEE board, and which has a function of more effectively reducing power consumption when setting a disconnect mode or a suspend mode. .

In the network interface according to claim 1, in addition to the active mode in which data is exchanged with the connected device, the disconnect mode in which the device is not connected, or the device is connected. A suspend mode in which data is not exchanged, and a network interface that executes processing according to a predetermined protocol when the setting or release of the disconnect mode or suspend mode is detected. A processing unit that performs data processing with a connected device, a clock generation unit (30) that outputs a reference clock signal for the processing unit, and a control circuit that is electrically connected to the clock generation unit, The control circuit does not depend on the clock signal and (i) disconnect mode or suspension Detects the setting of the mode, and outputs a first control signal for stopping the output of the clock signal to the clock generator, detects the release of the (ii) disconnect mode or the suspend mode, the clock to the clock generator to start the output of the signal, der outputs a second control signal of the inverted signal (CLKENB signal) of the first control signal is, the control circuit, the event detection circuit (21), the first two timing 2 and a first suspend mode control circuit (22, 23) for outputting control signals, and the event detection circuit is composed of a logic circuit independent of a clock signal, An event detection signal (EV signal) that switches to “L” when the suspend mode is set and to “H” when the suspend mode is set is output. The first and second suspend mode control circuits are respectively a logic circuit that does not depend on a clock signal, a two-input one-output OR gate (221, 234), a latch circuit (222, 235), and a two-input one-output AND gate ( 223, 233), and at one input terminal of the OR gate, a first signal (LPS signal) that becomes “H” when data is exchanged with a connected device is supplied to the OR gate. The event detection signal is input to the other input terminal from the processing unit, the output terminal of the OR gate is connected to the enable terminal E of the latch circuit, and the data terminal of the latch circuit A signal of “H” is inputted to D, and a mode selection signal which becomes “H” at the time of selection is applied to the reset terminal RB of the latch circuit and one input terminal of the AND gate. In the first suspend mode control circuit (22), the inverted data output terminal QB of the latch circuit is connected to the other input terminal of the AND gate (223). The 2-suspend mode control circuit (23) further includes a count circuit that functions as a timer. The data output terminal Q of the latch circuit is connected to the reset terminal RB of the count circuit. After reset, the “L” signal output after counting for a predetermined time is input to the other input terminal of the AND gate (233), and is included in the first and second mode control circuits. The latch circuit of one control circuit to which the mode selection signal of “H” is input is set, and the control circuit to which the latch circuit is set is set to “H”. The latch circuit is enabled by the output signal of the OR gate in response to an input of one signal or an event detection signal, and immediately after the predetermined time elapses, the AND gate does not depend on the clock signal. 2 control signals are output .

In the network interface according to claim 1, when the disconnect mode or the suspend mode is canceled, the second control signal that causes the clock signal generation unit to start outputting the clock signal is output immediately or after a predetermined time has elapsed. First and second suspend mode control circuits are provided. The latch circuit of one control circuit is set in response to the input of the “H” mode selection signal, and the set control circuit of the latch circuit does not depend on the clock signal and the first signal or the event signal The switching from “L” to “H” can be detected, and the second control signal can be output. Since the control circuit does not require a clock signal to detect the release of the mode, the power consumption of the interface can be reduced when the disconnect mode or the suspend mode is set.

(1) Summary of the Invention The network interface of the present invention has at least one of a disconnect mode and a suspend mode in addition to the active mode, and is scheduled when the disconnect mode or the suspend mode release condition is satisfied. A network interface that executes start-up processing according to the protocol of IEEE 1394. a network interface that conforms to the standard of a, operates without depending on the clock signal, and stops at least a part of the drive clock generation circuit included in the network interface according to the setting of the disconnect mode or the suspend mode, A drive control circuit is provided that causes the stopped clock generation circuit to operate again when the disconnect mode or suspend mode release condition is satisfied.

  By adopting the above configuration, it is possible to reduce the waste of power in the clock signal generation circuit and to effectively reduce the power consumption of the interface when setting the disconnect mode and the suspend mode.

  Hereinafter, the network interface of the present invention having the above features is referred to as IEEE 1394. An embodiment applied to the bus system a will be described with reference to the accompanying drawings.

(2) Embodiment FIG. 1 shows IEEE1394. Which is an embodiment of a network interface of the present invention. a host computer 100 provided with an interface board (hereinafter simply referred to as an IEEE board) 1 compliant with a, and a printer 500 equipped with the same or different IEEE board. 1 is a diagram showing a configuration of a network connected by a standard cable (hereinafter referred to as IEEE cable) 150 conforming to a. FIG.

  When the computer 100 and the printer 200 are powered on, each IEEE board is connected to the IEEE1394. Network recognition processing is executed according to the protocol specified in a.

  In the figure, the IEEE board 1 is described as connecting the computer 100 and the printer 500, but the interface board can also be applied to other devices such as a storage device and a digital video camera. For example, a storage device including the interface board 1 can be connected to the computer 100. Examples of the storage device include a hard disk, a CD / DVD drive, and an MO drive.

<2-1> IEEE Board Hereinafter, the IEEE board 1 included in the computer 100 will be described. FIG. 2 is a configuration diagram showing a part related to the IEEE board 1 which is an embodiment of the interface of the present invention, in the internal circuit of the computer 100. The IEEE board 1 is connected to the PCI bus 6. In addition to the IEEE board 1, a central processing unit (CPU) 8 of the computer 100 main body is connected to the PCI bus 6 via a chip set (motherboard) 7.

    The IEEE board 1 includes a PHY chip 2, a LINK chip 3, a PCI I / F control circuit 4 that operates in accordance with OHCI (abbreviation of Open Host Controller Interface) Version 1.1, and a PCI register 5.

  The IEEE board 1 defines a disconnect mode and a suspend mode in addition to an active mode that is set when information such as packet data is exchanged with the printer 500. The disconnect mode is a mode that is set when the printer 500 is not connected to the IEEE cable 150. The suspend mode is a mode that is set when the printer 500 is connected to the IEEE cable 150 but packet data is not exchanged.

  The suspend mode is a control signal input to the PHY chip 2 by the CPU 8 via the chip set 7, the PCI bus 6, the DMA 4a of the PCI I / F control circuit 4, and the LINK chip 3, specifically, This is also set according to the D3 state setting signal output by the driver for power saving control compliant with the PCI Power management standard.

  The return time defined in the D3 state in the PCI Power management standard is 10 ms. As will be described in detail below, in the IEEE board 1, as the suspend mode, it takes time to return, but a sleep mode that maximizes the power saving effect by completely stopping the clock generation mechanism including the PLL circuit can be set. . However, even when the sleep mode is selected, the time required for the clock generation mechanism to operate again stably is about several hundred μs to several ms. The release process can be completed. In this way, the IEEE board 1 ensures high versatility by eliminating the need to define a special protocol when used.

  The setting of the active mode, the disconnect mode, and the suspend mode is executed in the PHY chip 2 of the IEEE board 1. The PHY chip 2 includes a cable I / F 11 and a digital control unit 20 that processes a signal output from the cable I / F 11.

  The cable I / F 11 includes transmission / reception data, a connect detection signal that is in an asserted state (Low) when the opposite printer 500 is connected, and a Bias_ detection that is in an asserted state (High) when exchanging packet data. Various signals including the signal are output to the digital control unit 20.

  The digital control unit 20 sets the disconnect mode, the suspend mode, and the active mode according to the values of the connect detection signal and the Bias_ detection signal. FIG. 3 is a diagram for explaining mode transition. When the connection detection signal detected from the cable I / F 11 is in the negated state, the digital control unit 20 sets the disconnect mode. When the Bias_detection signal remains negated and the connect detection signal switches to the asserted state, the suspend mode is set. If the Bias_detection signal is switched to the asserted state when setting the suspend mode, the mode shifts to the active mode. Conversely, if the Bias_detection signal switches to the negated state when setting the active mode, the suspend mode is set. If the connect detection signal is switched to the negated state when the suspend mode is set, the disconnect mode is set.

  The IEEE board 1 will be described with reference to FIG. 2 again. The IEEE board 1 includes two suspend modes that can be selected by the BIOS 7a included in the chip set 7. The two suspend modes are a doze mode and a sleep mode.

  In the doze mode, the IEEE PHY chip of the IEEE board 1 is connected to the IEEE1394. A disconnect mode or a suspend mode that conforms to the standard of a is set, and a part of the clock generation mechanism in the PHY chip is stopped, so that unnecessary power in the clock generation mechanism is set when a mode other than the active mode is set. It is a mode for reducing consumption, and is characterized in that it can be restarted quickly, although its power saving efficiency is inferior to that of the sleep mode described below. For example, by stopping / restarting the clock generation mechanism other than the PLL circuit that requires time (from several hundred μs to several ms) for recovery, restart within the recovery time (200 μs) of the D2 state compliant with the PCI Power management standard It can be set to complete the process.

  In the sleep mode, the PHY chip of the IEEE board 1 is connected to the IEEE1394. This is a mode in which the clock generation mechanism inside the PHY chip is completely stopped at the same time as setting the disconnect mode or the suspend mode in conformity with the standard a, and the most wasteful power consumption when setting modes other than the active mode. It can be suppressed. However, for the convenience of completely stopping the clock generation mechanism, for example, it takes a certain time (several hundred μs to several ms) to generate a clock signal having a stable frequency.

  The chip set 7 is provided with a BIOS 7a that defines the contents of initial settings to be executed when the computer 100 is started. By selecting data in the BIOS 7a, the sleep mode and the doze mode are set when the computer 100 is started. Which of these can be used as the suspend mode can be set. The setting is stored as a 2-bit suspend mode setting signal in the PCI register 5 via the PCI I / F control circuit 4 when the computer 100 is activated.

  The PCI register 5 outputs the lower 1 bit of the stored 2-bit suspend mode setting signal to the PHY chip 2 as a sleep mode setting signal and outputs the upper 1 bit to the PHY chip 2 as a doze mode setting signal. These two signals take exclusive values, and when one is “H” (meaning setting), the other is set to “L” (meaning cancellation). That is, when the sleep mode is executed as the suspend mode, the sleep mode setting signal is set to “1” and the doze mode setting signal is set to “0”. When the doze mode is set, the sleep mode setting signal is set to “0” and the doze mode setting signal is set to “1”.

<2-2> PHY Chip FIG. 4 is a diagram showing a detailed configuration of the PHY chip 2. The PHY chip 2 is roughly composed of an analog block 10, a digital control unit 20, and a clock generation unit 30.

  The analog block 10 includes a cable I / F 11, a reference voltage / current source 12 for driving the cable I / F 11, a PLL circuit 13, and a reference clock transmission source 14.

  The reference clock source 14 is a so-called oscillator and generates a low-frequency reference clock signal XCLK. The PLL circuit 13 multiplies the clock signal XCLK to generate a clock signal PLLCLK having a high frequency (usually 400 MHz). The clock generation unit 30 performs frequency division processing and the like from the clock signal PLLCLK, and generates several types of drive clock signals CLK used by the digital control unit 20. The digital control unit 20 operates based on the several types of drive clocks CLK, and stops the operation when the input of the several types of drive clock signals CLK is stopped. The clock generator 30 operates when the CLKENB signal from the digital control circuit 20 is “L”, and stops operating when the CLKENB is “H”. The PLL circuit 13 operates when the PLLENB signal from the digital control circuit 20 is “L”, and stops operating when the PLLENB is “H”.

  The digital control unit 20 includes an event detection circuit 21, a doze mode control circuit 22, a sleep mode control circuit 23, an OR gate 24, and an arbitration / encode / decode unit 25.

  The event detection circuit 21 outputs an “H” event signal when the state (mode) of the IEEE board 1 changes. The event detection circuit 21 will be described in detail later.

  The doze mode control circuit 22 operates when the doze mode is set as the suspend mode according to the setting of the BIOS 7a. When the suspend mode is set, the CLKENB signal is switched from “L” to “H” to generate the clock generator 30. Stop the operation. Further, when the suspend mode release condition is satisfied, that is, according to the change of the event signal output from the event detection circuit 21 and the LPS (Link Power Status) signal output from the LINK chip 3, The CLKENB signal is returned from “H” to “L”, and the clock generator 30 is operated again. The LPS signal is a signal indicating whether or not the LINK chip 3 is operating normally, and is a signal set to “H” when the LINK chip 3 is operating. The dose mode control circuit 22 will be described in detail later.

  The sleep mode control circuit 23 operates when the sleep mode is set as the suspend mode according to the setting of the BIOS 7a. When the suspend mode is set, the CLKENB signal output to the clock generation unit 30 and the PLL circuit 13 are set. Both of the PLLENB signals to be output to are switched from “L” to “H” to stop the operation of the clock generator 30 and the PLL circuit 13. On the other hand, when the suspend mode is released, that is, the CLKENB signal and PLLENB signal are changed from “H” in accordance with the change of the event signal output from the event detection circuit 21 and the LPS signal output from the LINK chip 3. Then, the clock generator 30 and the PLL circuit 13 are operated again. The sleep mode control circuit 23 will be described in detail later.

  The OR gate 24 is a gate for adjusting the CLKENB signal output from the doze mode control circuit 22 and the sleep mode control circuit 23. The output from the effective mode control circuit is used as the CLKENB signal. The data is output to the clock generation unit 30. The sleep mode control circuit 23 always outputs a PLLENB signal of “L” to the PLL circuit 13 when the doze mode is set.

  The arbitration / encoding / decoding unit 25 operates based on several types of driving clock signals prepared by the clock generation unit 30, and IEEE1394. The transmission / reception data output from the cable I / F 11 of the analog block 10 is processed in accordance with a, and the processed data is output to the LINK chip 3.

<2-3> Cable I / F
FIG. 5 is a diagram illustrating a basic configuration of the cable I / F 11, an IEEE cable 150 configured by a twisted pair line, and a cable I / F 510 provided in the printer 500 that is an opposite node. The cable I / F 11 is roughly composed of a TpBias detection circuit and a transmission / reception circuit in addition to the connection detection circuit 111 and the Bias_detection circuit 112.

  The connection detection circuit 111 outputs a connection detection signal based on a change in potential difference between the TPA and TPA * twist lines of the IEEE cable 150 that occurs when the printer 500 is connected / disconnected to / from the IEEE cable 150. That is, when the printer 500 is connected to the IEEE cable 150, an “L” connection detection signal is output, and when the printer 500 is disconnected from the IEEE cable 150, an “H” connection detection signal is output.

  The Bias_ detection circuit 112 outputs a Bias_detection signal of “H” when a Bias signal applied to the cable is detected when exchanging information such as packet data, and the Bias signal is output. If not, a “L” Bias_detection signal is output. The configuration of the cable I / F 11 is all IEEE1394. This conforms to the provisions of a, and no further detailed explanation is omitted.

<2-4> Event Detection Circuit FIG. 6 is a diagram showing a configuration of the event detection circuit 21. The event detection circuit 21 includes three 2-input AND gates 211 to 213 and one 3-input OR gate 214. A connect detection signal is input to one input terminal of the AND gate 211 via an inverter, and a disconnect signal that is set to “H” when the disconnect mode is set is input to the other input terminal. The connect detection signal is input to one input terminal of the AND gate 212, and a suspend signal that is set to “H” when the suspend mode is set is input to the other input terminal. The suspend signal is input to one signal input terminal of the AND gate 213, and the Bias_detection signal is input to the other input terminal. The output terminals of the AND gates 211 to 213 are all connected to the input terminal of the OR gate 214.

  The event detection circuit 21 configured as described above outputs an “L” event signal when the disconnect mode and the suspend mode are set in the digital control unit 20. When the disconnect mode is set, if the printer 500 which is the opposite notebook is connected, that is, if the connect detection signal is switched from “H” to “L”, the event signal is changed from “L” to “H”. Switch. Further, when the printer 500 is removed at the time of setting the suspend mode, that is, when the connect detection signal is switched from “L” to “H”, or information such as packet data is exchanged with the printer 500. When the exchange is started, that is, when the Bias_detection signal is switched from “L” to “H”, the event signal is switched from “L” to “H”.

  When the IEEE board 1 has a plurality of ports, that is, when a plurality of cable I / Fs are included, event detection circuits 21 are provided corresponding to the cable I / Fs on a one-to-one basis, and each event detection circuit is provided. An AND gate that obtains the logical product of all event signals output from the AND gate may be provided, and the output of the AND gate may be output as a final event detection signal. In addition, the AND gate may employ a configuration for obtaining a logical product of a part of event signals output from each event detection circuit according to design convenience and necessity.

<2-5> Doze Mode Control Circuit The doze mode control circuit 22 functions effectively when the doze mode setting signal is “H”, and is associated with the setting of the disconnect mode or the suspend mode, that is, the LPS signal, When both event signals become “L”, the CLKENB signal is switched from “L” to “H” to stop the clock generator 30. On the other hand, when either the LPS signal or the event signal is switched from “L” to “H”, the CLKENB signal is switched from “H” to “L” to restart the clock generation unit 30. .

  FIG. 7 is a diagram showing a configuration of the dose mode control circuit 22. FIG. 8 is a time chart showing changes in the signal state from the setting of the disconnect mode or the suspend mode to the switching of the CLKENB signal accompanying the change in mode. The dose mode control circuit 22 includes a two-input one-output OR gate 221, a latch 222, and an AND gate 223. The LPS signal output from the LINK chip 3 is input to one input terminal of the OR gate 221, and the event signal output from the event detection circuit 21 is input to the remaining input terminals. The OR gate 221 outputs an “H” signal to the enable terminal E of the latch 222 when either the LPS signal or the event signal is switched to “H”. A doze mode setting signal is input to the reset terminal RB of the latch 222, and an “H” level signal is input to the data input terminal D.

  As shown in the time chart of FIG. 8, when the LINK chip 3 has stopped functioning and the disconnect mode or the suspend mode is set, that is, both the LPS signal and the event signal are “L”. In this case, the latch 222 outputs an “H” RSMB signal. In this case, an “H” CLKENB signal is output from the AND gate 223.

  When the exchange of data in the link is started and the LPS signal is switched from “L” to “H”, or the connection / disconnection of the opposing node and the start of exchange of packet data, the event signal is “L”. When switching from “H” to “H” (in the case of FIG. 8), the RSMB signal output from the data output terminal QB of the latch 222 switches from “H” to “L”. Accordingly, the CLKENB signal is switched from “H” to “L”, and the clock generator 30 is restarted.

<2-6> Sleep Mode Control Circuit The sleep mode control circuit 23 functions effectively when the sleep mode setting signal is “H”, and is associated with the setting of the disconnect mode or the suspend mode, that is, the LPS signal, When both the event signals become “L”, the CLKENB signal and the PLLENB signal are switched from “L” to “H” to stop the clock generator 30 and the PLL circuit 13. On the other hand, when either the LPS signal or the event signal is switched from “L” to “H”, first, a PLL circuit that takes time to start outputting a clock signal with a stable frequency after startup. After switching the PLLENB signal to 13 from “H” to “L” and restarting the PLL circuit 13, the timer waits for the above-mentioned time required for starting the PLL circuit 13 by a timer and then changes the CLKENB signal from “H” to “L”. And the clock generator 30 is restarted.

  FIG. 9 is a diagram illustrating a configuration of the sleep mode control circuit 23. The sleep mode control circuit 23 includes a count circuit 231 that functions as a timer for a predetermined time, a flip-flop 232, a latch 235, AND gates 233 and 236, and OR gates 234 and 237.

  The count circuit 231 has a plurality of flip-flops connected in series, and the clock signal XCLK output from the reference clock source 14 is input as a clock signal (enable signal). The RSM signal output from the output terminal Q of the latch 235 is input to the reset terminal RB of the count circuit 231. The output QB of the count circuit 231 is input to the clock terminal CK of the flip-flop 232, and the signal from the data output terminal D of the latch 235 is input to the reset terminal RB. An “H” signal is input to the data input terminal D. The data output terminal QB of the flip-flop 232 is connected to one input terminal of the 2-input AND gate 233. A sleep mode setting signal is input to the remaining input terminals of the AND gate 233. The CLKENB signal is output from the output terminal of the AND gate 233.

  The LPS signal is input to one input terminal of the 2-input OR gate 234, and the event signal is input to the remaining input terminals. The output terminal of the OR gate 234 is input to the clock terminal CK of the latch 235. A sleep mode setting signal is input to the reset terminal RB of the latch 235, and an “H” signal is input to the data input terminal D. An RSMB signal is output from the output terminal QB of the latch 235. The RSMB signal is input to one input terminal of the 2-input AND gate 236, and the sleep mode setting signal is input to the remaining input terminals. The output terminal of the AND gate 236 is connected to one input terminal of the two-input OR gate 237, and the dose mode setting signal is input to the remaining input terminals. The PLLENB signal is output from the output terminal of the OR gate 237.

  FIG. 10 is a time chart showing changes in the signal state from the setting of the disconnect mode or the suspend mode to the switching of the CLKENB signal and the PLLENB signal accompanying the change of the mode. When the sleep mode setting signal is set to “H”, no data is exchanged in the link, and the disconnect mode or the suspend mode is set, that is, the LPS signal. When the event signal is “L”, the data output terminal Q of the latch 235 outputs an “L” RSM signal, and the data output terminal QB outputs an “H” RSMB signal. In this case, the AND gate 233 outputs an “H” CLKENB signal, and the OR gate 237 outputs an “H” PLLENB signal.

  When the exchange of data within the link is started and the LPS signal is switched from “L” to “H”, or when the opposing node is connected / detached and the exchange of packet data is started, the event signal is “L”. When switching from “H” to “H” (in the case of FIG. 10), the RSMB signal output from the data output terminal QB of the latch 235 switches from “H” to “L”. Along with this, the PLLENB signal is switched from “H” to “L”, and the PLL circuit 13 is restarted.

  Further, the RSM signal output from the data output terminal Q of the latch 235 switches from “L” to “H”, and starts the count circuit 231. After the clock signals are cycled by the number of flip-flops included in the count circuit 231, the CLKENB signal output from the AND gate 233 is switched from “H” to “L”, and the clock generator 30 is restarted. Thus, the count circuit 231 functions as a timer. Note that the number of flip-flops included in the count circuit 231 is a number that delays the switching timing of CLKENB by the time required for the PLL circuit 13 to start and to output a stable PLLCLK.

  In the IEEE board 1 described above, the doze mode or the sleep mode is selected as the suspend mode according to the setting of the BIOS 7a. Further, a configuration is adopted in which one of the selected modes is set in accordance with a D3 state setting signal compliant with the PCI Power management standard. However, regardless of which mode is set as the suspend mode by the BIOS 7a, the sleep mode is set according to the D3 state setting signal conforming to the PCI Power management standard, and the doze mode is set according to the D2 state setting signal. You may employ | adopt the structure to do.

IEEE 1394. It is a figure which shows an example of the network using the bus system of a. It is a figure which shows the structure in the computer centering on the IEEE board. It is a figure for demonstrating mode switching. It is a figure which shows the structure of a PHY chip | tip. It is a figure which shows the structure of cable I / F. It is a figure which shows the structure of an event detection circuit. It is a figure which shows the structure of a dose mode control circuit. It is a time chart showing the signal in a dose mode control circuit. It is a figure which shows the structure of a sleep mode control circuit. It is a time chart showing the signal in a sleep mode control circuit.

Explanation of symbols

  1 IEEE board, 2 PHY chip, 3 LINK chip, 4 PCI I / F control circuit, 4a DMA, 5 PCI register, 6 PCI bus, 7 chipset, 7a BIOS, 8 CPU, 11 cable I / F, 13 PLL circuit , 14 reference clock source, 20 digital control circuit, 21 event detection circuit, 22 dose mode control circuit, 23 sleep mode control circuit, 24 OR gate, 30 clock generation unit, 100 computer, 500 printer.

Claims (1)

In addition to the active mode in which data is exchanged with the connected device, the disconnect mode in which the device is not connected, or the device is connected but no data is exchanged A network interface that executes processing according to a defined protocol when detecting the setting or release of the disconnect mode or the suspend mode.
A processing unit that performs data processing with a connected device, a clock generation unit (30) that outputs a reference clock signal for the processing unit, and a control circuit that is electrically connected to the clock generation unit. And
The control circuit does not depend on the clock signal,
(i) detecting the setting of the disconnect mode or the suspend mode, and outputting a first control signal for causing the clock generator to stop outputting the clock signal;
(ii) detecting the release of the disconnect mode or the suspend mode and outputting a second control signal (CLKENB signal) that is an inverted signal of the first control signal that causes the clock generator to start outputting the clock signal. Oh it is,
The control circuit includes an event detection circuit (21) and first and second suspend mode control circuits (22, 23) that output the second control signal at two timings,
The event detection circuit is composed of a logic circuit that does not depend on a clock signal, and outputs an event detection signal (EV signal) that switches to “L” when the disconnect mode or suspend mode is set and to “H” when the disconnect mode is set. Is,
Each of the first and second suspend mode control circuits includes a logic circuit that does not depend on a clock signal, a 2-input 1-output OR gate (221, 234), a latch circuit (222, 235), and a 2-input 1-output AND. Gates (223, 233), and
A first signal (LPS signal) that is “H” when data is exchanged with a connected device is input from the processing unit to one input terminal of the OR gate, and is input to the other input terminal. Is the above event detection signal input,
The output terminal of the OR gate is connected to the enable terminal E of the latch circuit.
A signal “H” is input to the data terminal D of the latch circuit,
A mode selection signal that is “H” at the time of selection is input to the reset terminal RB of the latch circuit and one input terminal of the AND gate.
In the first suspend mode control circuit (22), the inverted data output terminal QB of the latch circuit and the other input terminal of the AND gate (223) are connected,
The second suspend mode control circuit (23) further includes a count circuit functioning as a timer, the data output terminal Q of the latch circuit is connected to the reset terminal RB of the count circuit, and the count circuit From the reset, the “L” signal output after counting for a predetermined time is input to the other input terminal of the AND gate (233),
Among the first and second mode control circuits, the latch circuit of one control circuit to which the “H” mode selection signal is input is set, and the control circuit to which the latch circuit is set is set to “H”. The latch circuit is enabled by the output signal of the OR gate in response to the input of the first signal or the event detection signal, and immediately or after the predetermined time elapses, the AND gate does not depend on the clock signal. Outputting a second control signal;
A network interface characterized by that.

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