JPH03282738A - Information processor - Google Patents

Abstract

PURPOSE:To detect accidental malfunction or fault in microprocessor to construct the system with high reliability by synchronously operating two micro processors and permitting both to compare information outputted to buses. CONSTITUTION:The first microprocessor 1 for executing a regular processing, the second microprocessor 2 which synchronously operates with the first microprocessor 1 and which is for executing a supervisory processing and a comparison means 8 comparing information on the bus of the first microprocessor 1 and information on the bus of the second microprocessor 2 are provided. When a compared result noncoincident, it is judged that malfunction and the fault occur, and an exceptional processing request is transmitted. Thus, an information processor which can detect an error and whose reliability is high can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device using a microprocessor.

[Conventional technology]

Conventionally, in this type of information processing apparatus, microprocessors have not been duplicated. This is due to the fact that there were almost no microprocessors that supported duplexing.

[Problem to be solved by the invention]

As described above, in the past, since the microprocessors were not duplicated, there was a drawback that accidental malfunctions or failures inside the microprocessors could not be detected.

The present invention has been made to improve upon these conventional drawbacks, and its purpose is to provide a highly reliable information processing device that is capable of detecting errors.

[Means to solve the problem]

The information processing device of the present invention includes a first microprocessor for performing normal processing, a second microprocessor that operates in synchronization with the first microprocessor and performs monitoring processing, and a first microprocessor for performing monitoring processing. Comparing means for comparing information on the bus of the microprocessor and information on the bus of the second microprocessor, and configured to issue an exception handling request when the comparison result of the comparing means does not match. It has become.

The comparing means compares information on the data bus of the first microprocessor with information on the data bus of the second microprocessor when the first microprocessor outputs information to the data bus. or to compare the information on the first microprocessor's address bus with the information on the second microprocessor's address bus when the first microprocessor initiates a bus cycle. It's okay to be.

[For production]

When processing is performed in the first microprocessor, the second microprocessor is operated in synchronization with the processing, and the comparison means compares information on the bus (data bus or address bus) of the first microprocessor with the information on the second microprocessor. and the information on the microprocessor bus (data bus or address bus), and if the comparison results do not match, it is determined that a malfunction or failure has occurred, and an exception handling request is sent.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of the present invention. In the information processing apparatus shown in FIG. 1, in addition to the microprocessor 1 that performs normal processing, a monitoring microprocessor 2 is provided, and two general-purpose microprocessors 1 and 2 are operated synchronously. Duplication of microprocessors has become possible.

An address bus 101, a data bus 102, and a control signal bus 103 are connected to the microprocessor 1 that performs normal processing. Part of the address bus 101 is also given to the decoding circuit 9, and information on the control signal bus 103 and the control signal bus 103 are connected to the microprocessor 1. Combined with 4 read-only memories and 5 read-write memories
, each select signal 110, 111 of the input/output control unit 6
, 112 are output. Further, the address bus 101 and the data bus 102 are also connected to the read-only memory 4, the read/write memory 5, and the input/output control unit 6. The decoding circuit 9 includes the microprocessor 1
A part of address bus 101 and control signal bus 1 outputted by
03 and generates a signal 115 for controlling the bus cycle activated by the microprocessor 1.

Further, a clock signal 120 from the clock generation circuit 3 is supplied to the microprocessor 1 and the decoding circuit 9.
Furthermore, a reset signal 121 and an interrupt request signal 122 are input to the microprocessor 1 from the outside.

Furthermore, a signal 115 for controlling the bus cycle started by the microprocessor 1 is input to the monitoring microprocessor 2, and the data bus 202 of the microprocessor 2 is connected to the buffer circuit 7 and the comparison circuit 8. It is connected to the.

In addition, the microprocessor 2 also has a clock signal 120, a reset signal 121, and the like as well as the microprocessor 1.
and an interrupt request signal 122 are input. Note that the address bus 20 of the microprocessor 2
1. The control signal bus 203 is not connected anywhere.

Next, the operation of the information processing apparatus having such a configuration will be explained.

Decode circuit 9 determines whether a bus cycle of microprocessor 1 is an input or an output based on information from control signal bus 103.

[If the bus cycle indicates an input, the decode circuit 9 outputs a true control input signal 113. When the control input signal 113 is true, the buffer circuit 7 transfers information on the data bus 102 read from the read-only memory 4, the read/write memory 5, or the input/output control section 6 to the data bus 202 of the microprocessor 2. At this point, microprocessor 2 is connected to data bus 2.
Import the information on 02. This operation causes the microprocessor 2 to control the address bus 201 and the control signal bus 2.
To obtain information equivalent to the information obtained by the microprocessor 1 without using the microprocessor 03.

On the other hand, decoding circuit 9 outputs a true control input signal 114 when information from control signal bus 103 indicates that the bus cycle is an output. When the control input signal 114 is true, the comparator circuit 8 compares the information on the data bus 102 output by the microprocessor 1 with the information on the data bus 202 output by the microprocessor 2. As a result of this comparison, if there is a mismatch, the comparison circuit 8 sets the abnormality occurrence notification signal 123 to true.

In this way, microprocessor 2 executes the same instruction at the same timing in synchronization with microprocessor 1, but it is difficult to detect that the information on the data bus output by the two microprocessors is inconsistent. This makes it possible to detect the occurrence of an accidental malfunction or failure within the microprocessor 1 or the microprocessor 2, and issue an exception handling request to a higher-level device (not shown).

FIG. 2 is a block diagram of a second embodiment of the invention. Note that in FIG. 2, the same parts as in FIG. 1 are given the same reference numerals.

In the first embodiment, the address bus 201 and control signal bus 203 of the microprocessor 2 are not connected anywhere, and the data bus 201 is connected to the comparator circuit 8. The information on the data bus 102 output by the processor 1 and the information on the data bus 202 output by the microprocessor 2 are compared, but in the second embodiment, as shown in FIG. In this case, the address bus 201 is connected to the comparison circuit 8 instead of the data bus 202 of the microprocessor 2, and the address bus 101 is connected to the comparison circuit 8 instead of the data bus 102 of the microprocessor 1.
I am trying to connect to.

As a result, the comparison circuit 8 compares the information on the address bus 101 of the microprocessor 1 and the information on the address bus 201 of the microprocessor 2 only when the microprocessor 1 starts a bus cycle.

That is, in the second embodiment, decoding circuit 9 outputs true control input signal 114 when information from control signal bus 103 indicates that a bus cycle is being activated. When the control input signal 114 is true, the comparison circuit 8 compares the information on the address bus 101 outputted by the microprocessor 1 with the information outputted on the address bus 201 outputted by the microprocessor 2. As a result of this comparison, if there is a mismatch, the comparison circuit 8 sets the abnormality occurrence notification signal 123 to true.

In this way, microprocessor 2 executes the same instruction at the same timing in synchronization with microprocessor 1, but it is difficult to detect that the information on the address buses output by the two microprocessors is inconsistent. It is possible to detect the occurrence of an accidental malfunction or failure within the microprocessor 1 or microprocessor 2 and issue a fatal exception handling request to a higher-level device (not shown). Become.

[Effects of the Invention] As explained above, according to the present invention, two microprocessors are operated synchronously, and the information that the monitoring microprocessor outputs to the bus and the processing microprocessor outputs to the bus. Since the information is compared with the information provided by the microprocessor, it is possible to detect an accidental malfunction or failure within the microprocessor, and a highly reliable system can be constructed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a first embodiment of an information processing apparatus according to the present invention, and FIG. 2 is a block diagram of a second embodiment of the information processing apparatus according to the present invention. In the figure, 1.2...Microprocessor, 3...Clock generation circuit, 4...Read-only memory, 5...Readable/writable memory, 6...I/O control unit, 7...Buffer Circuit, 8... Comparison circuit, 9... Decoding circuit.

Claims (1)

[Claims] 1) a first microprocessor for performing normal processing; a second microprocessor for operating in synchronization with the first microprocessor and performing monitoring processing;
and a comparison means for comparing information on the bus of the second microprocessor and information on the bus of the second microprocessor, and transmits an exception handling request when the comparison result in the comparison means is a mismatch. An information processing device characterized by: 2) The comparing means compares the information on the data bus of the first microprocessor and the information on the data bus of the second microprocessor, and the first microprocessor outputs the information to the data bus. 2. The information processing apparatus according to claim 1, wherein the comparison is performed only when the information processing apparatus performs the comparison. 3) The comparing means compares information on the address bus of the first microprocessor and information on the address bus of the second microprocessor, and when the first microprocessor starts a bus cycle; 2. The information processing apparatus according to claim 1, wherein the information processing apparatus is configured to compare only the information processing apparatus.