JPH01154202A - Duplex process controller - Google Patents

Duplex process controller

Info

Publication number
JPH01154202A
JPH01154202A JP62314606A JP31460687A JPH01154202A JP H01154202 A JPH01154202 A JP H01154202A JP 62314606 A JP62314606 A JP 62314606A JP 31460687 A JP31460687 A JP 31460687A JP H01154202 A JPH01154202 A JP H01154202A
Authority
JP
Japan
Prior art keywords
arithmetic
systems
collation
calculation
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62314606A
Other languages
Japanese (ja)
Inventor
Tadatoshi Yamanishi
山西 忠敏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62314606A priority Critical patent/JPH01154202A/en
Publication of JPH01154202A publication Critical patent/JPH01154202A/en
Pending legal-status Critical Current

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  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
  • Safety Devices In Control Systems (AREA)

Abstract

PURPOSE:To assure the simultaneous property of the control arithmetic actions, etc., by transmitting the arithmetic end signal of one of two systems when the arithmetic operation of the other system is through and performing the collation between both systems in response to said arithmetic end signal to send back the result of the collation in a duplex process control system. CONSTITUTION:Two systems A and B are kept under the control and holding states respectively. When the arithmetic operation is through with the system A, this end state is transmitted to a diagnosing part 2B of the system B by means of an interlock signal 13B. Receiving the signal 13B, the system B performs the collation of arithmetic results between both systems. When this collation is over, the system B transmits an interlock signal 13A showing the end of collation to the system A. Both systems receive the collation end signals respectively and carry out the arithmetic operations of the following cycles. Thus both systems start the control arithmetic in the same timing and therefore assure the simultaneous property of both arithmetic results despite the transient changing state of a plant 7.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明はプロセス制御全般に適用される2重化構成さ
れたプロセス制御装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a process control device with a duplex configuration that is applied to general process control.

〔従来の技術〕[Conventional technology]

第2図は例えば特開昭59−2162号公報に記載され
た従来の2重化されたプロセス制御装置のブロック構成
図である。
FIG. 2 is a block diagram of a conventional duplex process control device described in, for example, Japanese Unexamined Patent Publication No. 59-2162.

同図において、(IA)はA系の演算部、(IB)はB
系の演算部、(2A)はA系の診断部、(2B)はB系
の診断部をそれぞれあられす。診断部(2A) 、 (
2B)からは、おのおのの系の診断結果(3A) 、 
(3B)が切換リレー(4)に出力される。またおのお
の系の操作出力は演算部(IA) 、 (IB)からそ
れぞれ操作出力(5A) 、 (5B) として切換リ
レー(4)の接点に出力され、診断結果(3A) 、 
(3B)に応じて切換リレー(4)により切換えられ、
最終出力(6))としてプラント(7)に送られる。
In the same figure, (IA) is an A-system calculation unit, and (IB) is a B-system calculation unit.
The arithmetic unit of the system, (2A) is the diagnostic unit of the A system, and (2B) is the diagnostic unit of the B system. Diagnosis department (2A), (
From 2B), the diagnosis results for each system (3A),
(3B) is output to the switching relay (4). In addition, the operation outputs of each system are output from the calculation units (IA) and (IB) as operation outputs (5A) and (5B), respectively, to the contacts of the switching relay (4), and the diagnostic results (3A) and
(3B) is switched by the switching relay (4),
The final output (6)) is sent to the plant (7).

プラント(7)からの出力はそれぞれ入力信号(8A)
 、 (8B) として演算部(IA) 、 (IB>
に供給される。また最終出力(6)はリードバック入力
信号(IOA) 、 (IOB) としてそれぞれ演算
部(IA) 、 (IB)に供給される。診断部(2A
) 、 (2B)からは現在のおのおのの系の状態を示
すステータス信号(lla)。
Each output from the plant (7) is an input signal (8A)
, (8B) as the arithmetic unit (IA), (IB>
is supplied to Further, the final output (6) is supplied to the calculation units (IA) and (IB) as readback input signals (IOA) and (IOB), respectively. Diagnosis department (2A
), and from (2B) is a status signal (lla) indicating the current state of each system.

fllb)が出力され、リレ一部(12)に供給される
fllb) is output and supplied to the relay part (12).

次に動作について説明する。A系演算部(1八)および
B系演算部(IB)はプラント(7)からの入力信号(
8八) 、 (8B)を読み込み、同一の制御演算を実
行する。そしていずれか一方の系がプロセスに対して演
算結果を出力する。
Next, the operation will be explained. The A system calculation unit (18) and the B system calculation unit (IB) receive input signals (
88) and (8B) and execute the same control calculation. Then, one of the systems outputs the calculation result to the process.

一方制御装置の最終出力(6)はプラント(7)に与え
られると同時にA系演算部(IA)、B系演算部(IB
)にもリードバック信号(IOA) 、 (li)  
として読み返される。ここで、待機系の系がこのリード
バック信号と自己の演算結果とを照合し、不一致か否か
を検出する。仮に待機系がB系であってB系診断部(2
B)が不一致と判断した場合には不一致を示すステータ
ス信号(IIB)をリレ一部(12)に送り、2重系の
いずれか一方に故障の生じたことを外部に伝える。
On the other hand, the final output (6) of the control device is given to the plant (7), and at the same time the A system calculation section (IA) and the B system calculation section (IB
) also has a readback signal (IOA), (li)
be reread as. Here, the standby system compares this readback signal with its own calculation result and detects whether there is a mismatch. Suppose that the standby system is B system and the B system diagnosis section (2
If it is determined that B) does not match, a status signal (IIB) indicating the mismatch is sent to the relay part (12) to notify the outside that a failure has occurred in either one of the duplex systems.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の2重化プロセス制御装置は以上のように構成され
ているため、A系とB系の演算の同時性が保証されてい
なかった。そこでプラントが過渡変化している場合には
A系、B系の演算結果が不一致となることが多く、系の
切換えが頌緊におこってしまう等の問題点が声った。
Since the conventional duplex process control device is configured as described above, the simultaneity of calculations in the A system and the B system cannot be guaranteed. Therefore, when the plant is undergoing transient changes, the calculation results of the A system and the B system often do not match, and problems have been raised, such as the system switching occurring too quickly.

この発明は上記のような問題点を解消するためになされ
たもので、プラントが過渡変化している時でもA系、B
系の演算結果の同時性を保証することができ、しかも不
要な系の切換えを防止することのできる2重化プロセス
制御装置を得ることを目的とする。
This invention was made to solve the above-mentioned problems, and even when the plant is undergoing transient changes, the A system and B system
It is an object of the present invention to provide a redundant process control device that can guarantee the simultaneity of system calculation results and prevent unnecessary system switching.

〔問題点を解決するための手段〕[Means for solving problems]

この発明にかかる2重化プロセス制御装置は、2つの演
算系がプロセスに対し2重化され同一の制御演算を実行
し、いずれか一方の系が前記プロセスに対し演算結果を
出力し、他方の系がこれを自己の演算結果とを照合し不
一致か否かを検出する2重化プロセス制御装置において
、前記一方の系が演算を終了した時、前記他方の系に演
算終了の信号を送出する第1の手段と、前記演算終了の
信号に応答して前記他方の系が演算結果の照合を行い、
照合終了後に前記一方の系に対し照合終了の信号を送出
する第2の手段とを設けたものである。
In the duplex process control device according to the present invention, two calculation systems are duplicated for the process and execute the same control calculation, one of the systems outputs the calculation result to the process, and the other system outputs the calculation result to the process. In a duplex process control device in which the system compares the result with its own calculation result and detects whether there is a discrepancy, when the one system finishes the calculation, it sends a signal of completion of the calculation to the other system. the first means and the other system collate the calculation results in response to the calculation end signal;
and second means for sending a signal indicating completion of verification to the one system after completion of verification.

(作用〕 この発明では第1の手段がA系の演算を了した段階でB
系へ演算終了の信号を送出する。そして第2の手段が、
この信号を受けて演算結果の照合を行い、照合が完了し
たらA系に終了信号を送り返す。そしてA系、B系が同
時に次の同期の演算を実行開始し、両系の間でインター
ロック信号を付加し、これによりA系、B系の同時性を
保証することができ不要な系の切換えを防止できる。
(Operation) In this invention, the first means
Sends a computation end signal to the system. And the second means is
Upon receiving this signal, the calculation results are compared, and when the comparison is completed, a completion signal is sent back to the A system. Then, the A system and the B system simultaneously start executing the next synchronization calculation, and an interlock signal is added between the two systems, thereby guaranteeing the simultaneity of the A system and B system, and removing unnecessary systems. Switching can be prevented.

(実施例) 以下この発明の一実施例を第1図に基づいて説明する。(Example) An embodiment of the present invention will be described below with reference to FIG.

第1図はこの発明の一実施例を示す2重化プロセス制御
装置のブロック構成図である。
FIG. 1 is a block diagram of a duplex process control device showing one embodiment of the present invention.

なお、第2図に示す従来の装置の構成と同一部分には同
一符号を付しその詳細説明は省略する。
Components that are the same as those of the conventional device shown in FIG. 2 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

この発明では、A系とB系との演算の同時性を保証する
ためのインターロック信号(13A)をA系診断部(2
A)とB系演算部(IB)との間に、インターロック信
号(13B)をA系演算部(IA)とB系診断部(2B
)との間に供給する構成である。
In this invention, the interlock signal (13A) for guaranteeing the simultaneity of calculations in the A system and the B system is transmitted to the A system diagnostic section (2).
The interlock signal (13B) is connected between the A system calculation unit (IA) and the B system diagnostic unit (2B) between the A system calculation unit (IA) and the B system calculation unit (IB).
).

A系演算部(IA)およびB系演算部(IB)はプラン
ト(7)からの入力信号(8A) 、 (8B)を読み
込みおのおの同一の制御演算を実行する。今、仮にA系
が制御、B系が待機状態だと仮定する。A系の演算が終
了した段階でインターロック信号(13B)を使ってB
系の診断部(2B)へ、A系の演算終了を伝える。
The A-system calculation section (IA) and the B-system calculation section (IB) read input signals (8A) and (8B) from the plant (7) and each execute the same control calculation. Now, assume that system A is in control and system B is in standby mode. When the calculation of A system is completed, use the interlock signal (13B) to
Informs the system diagnosis unit (2B) that the calculation of system A has finished.

B系はこのインターロック信号(13B)を受けて、演
算結果の照合を行い照合が終了したら逆にA系へ照合終
了のインターロック信号(13A)を伝達する。
The B system receives this interlock signal (13B), collates the calculation results, and when the collation is completed, conversely transmits an interlock signal (13A) indicating the completion of the collation to the A system.

A系、B系はこの照合終了の信号を受けて次の周期の演
算を実行する。これによりA系、B系は同じタイミング
で制御演算を開始することになりプラント(7)が過渡
変化中であっても演算結果の同時性を保証できることに
なる。
The A system and the B system receive this verification end signal and execute the calculation for the next cycle. As a result, the A system and the B system start control calculations at the same timing, and even if the plant (7) is undergoing a transient change, the simultaneity of the calculation results can be guaranteed.

もし仮に演算結果が不一致となった場合にはステータス
信号(IIB)に基づいてリレ一部(12)を動作させ
、2重系のいずれか一方に故障の生じたことを外部に伝
達する。なお前述した実施例では少なくとも一方の系が
健全に動作している場合について説明したが、一方の系
が故障中の場合も考慮する必要がある。
If the calculation results do not match, the relay part (12) is operated based on the status signal (IIB), and the fact that a failure has occurred in one of the duplex systems is transmitted to the outside. In the above-described embodiments, the case where at least one system is operating normally has been described, but it is also necessary to consider the case where one system is in failure.

この場合、先の実施例で示したインターロック信号(1
3A) 、 (13B)が逆に健全な系に悪影響を与え
ないようにする必要がある。このため信号受信側でタイ
マー監視を行い一定時間過ぎても応答信号が返ってこな
い場合には次の周期の演算をはじめるようにしておく。
In this case, the interlock signal (1
It is necessary to prevent 3A) and (13B) from adversely affecting a healthy system. For this reason, a timer is monitored on the signal receiving side, and if a response signal is not returned after a certain period of time, calculations for the next cycle are started.

このようにすることにより一方の系が故障であっても他
方の系で制御を続行することができる。
By doing so, even if one system fails, control can be continued with the other system.

〔発明の効果〕〔Effect of the invention〕

以上説明したようにこの発明によれば、一方の系が演算
を終了した時他方の系に演算終了の信号を送出する第1
の手段と、この演算終了信号に応答して照合を行い照合
結果を送り返す第2の手段とを設けたため、制御演算の
同時性を保証することができるという効果がある。
As explained above, according to the present invention, when one system completes an operation, the first system sends an operation end signal to the other system.
Since the second means performs verification in response to the calculation end signal and sends back the verification results, it is possible to guarantee the simultaneity of the control calculations.

したがって安定した2重化プロセス制御装置を得ること
ができるという効果がある。
Therefore, there is an effect that a stable duplex process control device can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例にかかる2重化プロセス制
御装置のブロック構成図、第2図は従来の2重化プロセ
ス制御装置の構成を示すブロック構成図である。 (IA)はA系演算部、(IB)はB系演算部、(2A
)はA系診断部、(2B)はB系診断部、(3A)はA
系診断結果、(3B)はB系診断結果、(5A)はA糸
操作出力、(5B)はB糸操作出力、(6)は最終出力
、(7)はプラント、(8A) 、 (aa)はプラン
トからの入力信号、(IOA) 、 (10B)はリー
ドバック信号、(IIA) 、 (IIB)はステータ
ス信号、(12)はリレ一部、(13A)はA系インタ
ーロック信号、 (13B)はB系インターロック信号。 なお、図中、同一符号は同一または相当部分を示す。
FIG. 1 is a block configuration diagram of a duplex process control device according to an embodiment of the present invention, and FIG. 2 is a block configuration diagram showing the configuration of a conventional duplex process control device. (IA) is the A system calculation section, (IB) is the B system calculation section, (2A
) is the A-system diagnostic section, (2B) is the B-system diagnostic section, (3A) is the A-system diagnostic section.
System diagnosis result, (3B) is B system diagnosis result, (5A) is A thread operation output, (5B) is B thread operation output, (6) is final output, (7) is plant, (8A), (aa ) is the input signal from the plant, (IOA) and (10B) are the readback signals, (IIA) and (IIB) are the status signals, (12) is the relay part, (13A) is the A system interlock signal, ( 13B) is a B-system interlock signal. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] 2つの演算系がプロセスに対し2重化され同一の制御演
算を実行し、いずれか一方の系が前記プロセスに対し演
算結果を出力し、他方の系がこれと自己の演算結果とを
照合し不一致か否かを検出する2重化プロセス制御装置
において、前記一方の系が演算を終了した時前記他方の
系に演算終了の信号を送出する第1の手段と、前記演算
終了の信号に応答して前記他方の系が演算結果の照合を
行い、照合終了後に前記一方の系に対し照合終了の信号
を送出する第2の手段とを具備したことを特徴とする2
重化プロセス制御装置。
Two calculation systems are duplicated for a process and execute the same control calculation, one of the systems outputs the calculation result to the process, and the other system compares this with its own calculation result. In a duplex process control device for detecting a mismatch, the first means sends a computation end signal to the other system when the one system finishes computation, and responds to the computation end signal. and a second means for collating the calculation results by the other system and sending a signal indicating completion of the collation to the one system after the collation is completed.
Heavy duty process control equipment.
JP62314606A 1987-12-10 1987-12-10 Duplex process controller Pending JPH01154202A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62314606A JPH01154202A (en) 1987-12-10 1987-12-10 Duplex process controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62314606A JPH01154202A (en) 1987-12-10 1987-12-10 Duplex process controller

Publications (1)

Publication Number Publication Date
JPH01154202A true JPH01154202A (en) 1989-06-16

Family

ID=18055319

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62314606A Pending JPH01154202A (en) 1987-12-10 1987-12-10 Duplex process controller

Country Status (1)

Country Link
JP (1) JPH01154202A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0721106A (en) * 1993-06-30 1995-01-24 Nec Corp Network managing method
JP2014229198A (en) * 2013-05-24 2014-12-08 株式会社ケーヒン Multicore system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0721106A (en) * 1993-06-30 1995-01-24 Nec Corp Network managing method
JP2014229198A (en) * 2013-05-24 2014-12-08 株式会社ケーヒン Multicore system

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