JPH0795282B2 - Duplex microprocessor automatic switching device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention selectively and automatically switches a duplexed microprocessor to one input / output unit under optimum conditions.
The present invention relates to an automatic switching device for a duplicated microprocessor.

[Conventional technology]

FIG. 4 is a block connection diagram showing a conventional automatic switching device for a duplexed microprocessor. In the figure, reference numerals 12 and 13 denote microprocessors. Hereinafter, the microprocessor 12 is an operating system and the microprocessor 13 is a standby system. I will explain. Reference numeral 14 is a system bus for transmitting address, data, and command signals, 15 is a manual switch section, and 16 is a bus changeover switch which is switched in conjunction with the manual switch section 15 and is conceptually shown. 17 is a microprocessor
An input / output unit that sends and receives data and the like to either one of 12 and 13.

FIG. 5 is a block connection diagram specifically showing the bus changeover switch 16. The driver / receiver 7a corresponding to each signal of address, data and command is provided for each microprocessor 12 and 13 of the operating system and the standby system. 7b, 7c and 8a, 8b, 8c
And has a gate terminal for controlling operation and non-operation. 16A is a control switch for inputting a control signal to the gate terminal, which corresponds to the bus changeover switch 16 of FIG. 18 is an inverter for inputting a relative signal to the two gate terminals.

Next, the operation will be described. FIG. 4 shows a backup switching device, and an operating microprocessor.
12 operates through the bus changeover switch 16 while using the input / output unit 17. Now, when it is necessary to switch the microprocessor 12 to the standby system microprocessor 13 due to down or the like, the bus switch 16 is moved to the microprocessor 13 by operating the manual switch section 15.
Switch to the side. This microprocessor 13
To start the operation.

FIG. 5 shows this switching operation in detail. Here, by turning the control switch 16A on or off, the gate terminals of the drivers / receivers 7a to 7c and 8a to 8c are set to "1" and "0". 'As these drivers /
Through either the receiver 7a-7c or 8a-8c, the microprocessor 12 or 13 can exchange system data with the input / output unit 17.

[Problems to be Solved by the Invention]

Since the conventional automatic switching device for the duplexed microprocessor is configured as described above, each microprocessor 1
The switching connection to the input / output section 17 of 2, 13 is a manual switch section.
It must be performed manually by 15, and in this case, it is necessary to switch to the standby microprocessor 13 after confirming that the operating microprocessor 12 is down. When switching is performed, there was a problem that normal data could not be passed and the system went down.

The present invention has been made in order to solve the above problems, and when the down of the operating system microprocessor is detected, the input / output unit can be automatically switched and connected to the standby system microprocessor. At the same time, it is an object of the present invention to obtain an automatic switching device for a dual microprocessor in which two microprocessors can be operated in parallel at the same time.

[Means for Solving the Problems]

When the driver / receiver receives the selection command signal or the double command signal from the bus switching signal output circuit by the driver / receiver, the automatic switching device of the dual microprocessor according to the present invention responds to these command signals. And the bus of the input / output unit are connected, and by the access monitoring circuit, they are provided in the operating system microprocessor and the standby system microprocessor respectively, and while the signals for parallel operation are being output, A bus switching signal output circuit for outputting a second selection signal for selecting the standby microprocessor when detecting that the access of the microprocessor that has acquired access has exceeded the set time Is.

[Action]

The automatic switching device of the dual microprocessor according to the present invention is provided in each of the operating microprocessor and the standby microprocessor, and receives the selection command signal or the dual command signal from the bus switching signal output circuit. , The driver / receiver that connects the bus of the microprocessor and the bus of the input / output unit in accordance with these command signals, and the microprocessor of the operating system and the microprocessor of the standby system are provided respectively and should be operated in parallel. When outputting a signal and detecting that the access of the microprocessor that has acquired the access has exceeded the set time, a second selection signal for selecting the standby microprocessor is sent to the bus. By providing the access monitoring circuit for outputting to the switching signal output circuit, the dual system microprocessor It is possible to string processing is carried out.

Example of Invention

An embodiment of the present invention will be described below with reference to the drawings. First
In the figure, reference numeral 1 denotes a microprocessor selection circuit which outputs a signal for automatically selecting one of the microprocessors 12 and 13 in the backup mode. Reference numeral 9 is a selection switch for forcibly generating such a signal as an A master signal and a B master signal, 1a and 1b are down signals for operating and standby systems, and 1c is a reset signal. A manual / automatic selection circuit 2 receives the down signal 1a or 1b obtained from one of the switching control circuits 6a and 6b, and automatically switches in the backup mode. 10 is a manual / automatic changeover switch for manually setting the above manual / automatic changeover, 3 is a parallel / backup selection circuit for selecting each parallel / backup operation mode of the microprocessors 12 and 13, and 11 is this selection changeover. A changeover switch 4 to be set is a bus changeover signal output circuit, which outputs a bus changeover signal for connecting one of the microprocessors 12 and 13 selected by the access signals 4a and 4b to the input / output unit 17 to the gate signal I, Output as J. 5a, 5b
Is an access monitoring circuit, which is in the parallel operation mode, and when the access (access signal 4a) of the microprocessor 12 which has acquired the access first exceeds the set time, the standby system microprocessor 13 inputs and outputs the input and output. The signal (gate signal J) to be connected to the section 17 is supplied to the bus switching signal output circuit 4
Is output through. 5c and 5d are acknowledge signals as response signals from the input / output section. The output side of the bus switching signal output circuit 4 is connected to the gate terminals of drivers / receivers 7a to 7c and 8a to 8c similar to those shown in FIG.

Next, the operation will be described with reference to the timing chart of FIG. First, when the microprocessor 12 is operating as an operating system and the access signal 4a becomes active (H level), the driver / receiver 7a
Gate signal I input to ~ 7c is active (L
Therefore, the drivers / receivers 7a to 7c are activated, and the address, data, and command signals on the microprocessor 12 side are input to the input / output unit 17. At this time, microprocessor selection circuit 1, manual /
In the signal line between the automatic selection circuit 2, the parallel / backup selection circuit 3 and the bus switching signal output circuit 4, since the microprocessor 12 is the operating system, the signals C, E and G are active (H level) during the T ₁ period. ). In this case, when it is detected that the microprocessor 12 is down at t ₁ , the microprocessor selection circuit 1 switches the microprocessor 13 which has been the standby system until then to the operation system, and the signals D, F, and H becomes active (H level), and the gate signal J becomes active (L level) by the transition of the access signal on the access signal 4b line to active. Accordingly driver 8a~8c is activated, the address, data, signals a command from the microprocessor 13 to the input-output unit 17, is supplied during the period T _2.
In this case, even if the microprocessor 12 returns to normal, the microprocessor 13 is still operating as an operating system, and if it is necessary to change the microprocessor 12 to the operating system, reset on the reset signal line. This is possible by activating the signal 1c and inputting it to the microprocessor selection circuit 1.

Next, the parallel operation mode will be described with reference to the timing chart of FIG. First, when both the microprocessors 12 and 13 need to access the input / output unit 17, the input / output unit 17 is accessed by the access signals 4a and 4b, and the acknowledge signal is received from the input / output unit 17 to Terminate access. At this time, any of the signals C, D, E, and F may be active, and since the signals are in the parallel operation mode, the output signals G, H of the parallel / backup selection circuit 3
Are both active (H level) during the T ₃ period. Then, during the T ₄ period, access to the input / output unit 17 of both the microprocessors 12 and 13 is overlapped, and the prefetching operation in the bus switching signal output circuit 4 causes the microprocessor 12 to be in advance.
Has obtained access to the input / output unit 17. At this time, for some reason, the microprocessor 12 requires a time longer than the normal access time to the input / output unit 17, and the access timers Ta and Tb in the access monitoring circuit 5a are required.
When the access timer Ta times out at time t ₂ (not shown), the signal K becomes active (L level), and the gate signal I becomes inactive (by the arbitration logic of the bus switching signal output circuit 4). (H level), the access right to the input / output unit 17 is passed to the microprocessor 13 which has been in the standby state until then. As a result, the gate signal J becomes active, and the microprocessor 13 is connected to the input / output unit 17. In this way, it is possible to prevent the monopolization of the input / output unit 17 by the one microprocessor 12 or 13 and the system down caused by the monopoly.

Although the active level is limited in the above embodiment,
The active level may be changed by changing the logic.

〔The invention's effect〕

As described above, according to the present invention, when the driver / receiver receives the selection command signal or the dual command signal from the bus switching signal output circuit, the bus and the input / output unit of the microprocessor are responded to in accordance with these command signals. In addition to connecting to the bus, the access monitoring circuit is provided for each of the operating system microprocessor and the standby system microprocessor to gain access first while the signals for parallel operation are being output. When it detects that the access time of the microprocessor is exceeding the set time,
Since the second selection signal for selecting the standby microprocessor is output to the bus switching signal output circuit, the function and processing speed of the system due to the parallel operation can be improved.

[Brief description of drawings]

FIG. 1 is a block connection diagram showing an automatic switching device of a duplexed microprocessor according to an embodiment of the present invention, and FIG. 2 is a timing chart showing signals of respective parts of the block in FIG. 1 in a backup / automatic switching mode, FIG. 3 is a timing chart showing signals of respective parts of the block in FIG. 1 in a parallel operation mode, FIG. 4 is a block connection diagram showing an automatic switching device of a conventional duplex microprocessor, and FIG. 5 is FIG. 3 is a block connection diagram showing details of a switching unit in FIG. 1 is a microprocessor selection circuit, 3 is a parallel / backup selection circuit, 4 is a bus switching signal output circuit, 5a and 5b are access monitoring circuits, 12 is an operating system microprocessor, 13
Is a standby microprocessor and 17 is an input / output unit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A microprocessor of an operating system and a microprocessor of a standby system, and a microprocessor selection circuit which outputs a selection signal for selecting the microprocessor of the standby system when down of the microprocessor of the operating system is detected. And a parallel / backup selection circuit for outputting a parallel operation instruction signal for switching these microprocessors from parallel operation to parallel operation, and when the selection signal from the microprocessor selection circuit is received, this selection is made. The first selection command signal for connecting the bus of the microprocessor and the bus of the input / output unit is output, and when the parallel operation instruction signal from the parallel / backup selection circuit is received, both of the microprocessors. The dual command signal that connects the bus of In an automatic switching device for a duplexed microprocessor having an output bus switching signal output circuit, each of the operating system microprocessor and the standby system microprocessor is provided with a bus switching signal output circuit. When a selection command signal or a dual command signal is received, a driver / receiver for connecting the bus of the microprocessor and the bus of the input / output unit according to these command signals, the microprocessor of the operation system, and the standby system. When each of the microprocessors, which is provided for each of the microprocessors, is outputting a signal for the parallel operation, and the microprocessor that has acquired the access first detects that the access exceeds the set time. ,
An automatic switching device for a duplexed microprocessor, comprising: an access monitor circuit for outputting a second selection signal for selecting the standby microprocessor to the bus switching signal output circuit.