JPH0220029B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Among dual system switching control devices, the present invention particularly relates to a device for controlling switching between operation and standby of a first and second central processing unit used for controlling an electronic exchange. The objective is to provide a device that is easy to manufacture and provides stable operation.

A conventional device is shown in FIG. 1 and 2 are first and second central processing units (hereinafter referred to as first and second CPUs); 3 and 4 are bus signal driver receivers for the first and second CPUs 1 and 2, respectively; 5 is a switching control device, 6 is an extended first and second CPU 1,
2 is a bus, 7 is an external device, and 8 is a control interface circuit interposed between the bus 6 and the external device 7. 9 and 10 are the first and second CPU1, respectively.
A signal line indicating the operating status (normal/failure) of 2, 1
1 and 12 are the driver receiver 3, respectively;
4 is a signal line for granting operation permission, and 13 is a connection line between the control interface 8 and the external device 7.

In the conventional device, the switching control device 5 connects the signal lines 9,
10 and detects a failure in the active CPU of the first and second CPUs 1 and 2, it disables the driver receiver of the CPU that had been the active system until then, and disabled the CPU that had been the standby system until then. This is a method of giving operation permission to the CPU driver receiver and switching to the active system. However, the bus signals of the first and second CPUs 1 and 2 operate at very high speeds, and connecting the two CPUs 1 and 2 and the control interface circuit 8 with cables, etc. It is accompanied by great technical difficulties such as mutual interference between the two, and extremely advanced manufacturing technology is required in order to obtain sufficient stability.

Therefore, the present invention provides the following advantages: by connecting the buses of the first and second central processing units to the operation/standby switching means via respective control interfaces,
An embodiment of the present invention, which avoids the problem of interference between the buses of the first and second central processing units, will be described below with reference to the drawings. Components having the same functions as those in FIG. 1 are given the same reference numerals and their explanations will be omitted.

14 and 15 are the first and second CPU1, respectively
2 is connected to the control interface circuit at the shortest distance; 16 and 17 are control signal buses of the control interface circuits 14 and 15, respectively; and 18 is a connection line 13 to the external device 7 connected to the control signal bus 16 or 17. Switches 19 and 20 are signal lines that indicate whether or not the first and second CPUs 1 and 2 are mounted, respectively, and are at logic level "L" in the mounted state, and at logic level "H" in the unmounted state. ”
It is in. 21 is a switching control device, which connects the signal lines 9,
10 and signal lines 19 and 20 and sends a signal instructing switching of the switch 8 to a switching control line 22.
Output via.

In this configuration, the first and second
The operating status of CPUs 1 and 2 is determined by connecting signal lines 9 and 10 to
Switching control device 21 corresponding to switching control device 5 in the figure
Up to the point of monitoring, FIG. 1 is the same as the conventional example, but since the overall configuration is different, the configuration will be explained in more detail along with its operation.

The outline of the switching control device 21 is that when the first CPU 1 of the active CPU, for example, fails, the control signal bus 1 that has been output from the control interface circuit 14 of the first CPU 1, which has been the active system until now, is activated.
6 to the connection line 13.
, the control signal bus 17 instead of the control signal bus 16
A specific example of this switching control device 21 is shown in FIG. 8. 23 is a manual changeover switch, and 24 is a monostable multivibrator, which outputs one pulse _P1 each time the manual changeover switch 23 is operated. 25 is a negative logic NAND gate, 26, 27,
28 is a positive logic AND gate, 29 and 30 are selector circuits that select one of the two inputs, 31 is an inverter, 32 is a D-type flip-flop with a preset function and a clear function, 33 is a positive logic NOR gate, and 34 is a power-on clear. The circuit generates one pulse P ₂ when the power is turned on. Note that, depending on the operating state of the first and second CPUs 1 and 2, both the signal lines 9 and 10 are inverted and switched to logic levels "L" and "H" during normal operation and during failure, respectively. When the control line 22 is at logic level "H", the switch 18 connects the control signal bus 16 and the connection line 13; when the switching control line 22 is at logic level "L", the switch 18 connects the control signal bus 17 and the connection line 13. Connecting.

Now, when the power is turned on with both signal lines 9 and 10 in the "L" state, a pulse _P2 is generated from the power-on clear circuit 34. Since signal lines 9 and 10 are both "L", the output of gate 25 is inverted to "H", and when pulse P ₂ occurs, gate 2
7 is pulse P. It is inverted to "H" for only ₂ periods and gate 3
Clear terminal of flip-flop 32 through 3
CL, the output of the flip-flop 32 becomes "H" level and the switching control line 22 becomes "H", so when the power is turned on, the switching device 18 connects the control signal bus 16 and the connection line 13 and switches the first Make CPU1 the active system and the second CPU2 the standby system. both
If both CPUs 1 and 2 are operating normally, the first CPU 1 always becomes the active system when the power is turned on, which is convenient for adjustments, etc.

In this state, the output of the gate circuit 28 is "L" and the selector circuits 29 and 30 are connected to the signal lines 9 and 1, respectively.
0 is output to the inverter 31 and gate 33. Further, if both the first and second CPUs 1 and 2 are in normal operation, the output of the gate 25 is "H", so the monostable multivibrator 24 generates the pulse P ₁ by operating the manual changeover switch 23.
This pulse P ₁ strikes the clock terminal CK of the flip-flop 32 via the gate 26. Then,
The output of the flip-flop 32 is inverted to "L", the switching control line 22 which was at "H" is inverted to "L", and the active system and standby system are switched. In this manner, if both CPUs 1 and 2 are operating normally, by operating the manual changeover switch 31, switching operations can be performed as necessary to inspect control signal lines and the like.

Next, when the first CPU 1 in the active system fails and the signal line 9 becomes "H", the output of the inverter 31 becomes "L", the preset terminal PR of the flip-flop 32 is always set, and the output of the flip-flop 32 becomes "L". Fixed to 2nd CPU
2 will be the operational system. Conversely, when signal line 9 becomes "L" and signal line 10 becomes "H", the output of gate 33 becomes "L", the clear terminal of flip-flop 32 is set, and the output is fixed at "H". The first CPU1 becomes the active system.

If one of the first and second CPUs 1 and 2 breaks down, it will be repaired, but for example, the first
Assuming that CPU1 has been repaired, the first
When the CPU 1 is not installed, the signal line 19 becomes "H".
If the second CPU 2 further fails in this state, the signal line 9 will naturally remain at "H" and the signal line 10 will remain at "H" level.
also becomes “H”. To explain the operation assuming that the selector circuits 29 and 30 are not switched by the gate 28, a set signal is input to both the preset terminal PR and the clear terminal CL of the flip-flop 32, the output becomes "H", and the unmounted side 1st of
CPU1 will be selected. This is very inconvenient.

By the way, even if the first and second CPUs 1 and 2 fail, they generally attempt to reprocess, and if the second CPU 2 attempts to restart, it will be inconvenient if it is not connected to the external device. Therefore, in this embodiment, such a case is also assumed.

When the signal lines 9 and 10 are both "H", the gate 28 detects this and outputs "H". On the other hand, the selector circuits 29 and 30 are connected to the signal line 1, respectively.
Since inputs 9 and 20 are selected, "H" on signal line 19 is transmitted to inverter 31 and sets preset terminal PR of flip-flop 32.
Therefore, the output becomes “L” and the second
CPU2 is selected. As a result, the second CPU2
will be able to easily attempt the restart process. Note that the above description also applies to the case where the signal lines 19 and 20 are interchanged.

As explained above, according to the present invention, the first and second
A control interface circuit is connected to each bus of the central processing unit of the controller, and a control signal bus is connected between each control interface circuit and an external device.
Since the control signal bus of the external device is connected to the control interface circuit of the central processing unit on the operating side by intervening the operation/standby switching means, the first and second central processing units and the control interface circuit are connected. The bus signal line connecting the first central processing unit and the control interface circuit can be connected to the second central processing unit and the control interface circuit. There is no mutual interference with bus signal lines, and stable operation can be expected. Since the operating speed of the signals handled by the switching means is considerably lower than that of the bus signal line connecting the central processing unit and the control interface circuit, sophisticated manufacturing technology is not required.

Furthermore, the configuration of the switching means is such that normally a selector circuit selects a signal representing the operating state of the first and second central processing units to control the flip-flop;
When one of the first and second central processing units fails, the other central processing unit is put into operation, and when one central processing unit is not installed and the other central processing unit fails, the selector is activated. Because the circuit was configured to switch to a signal representing the mounting state to control the flip-flop and put the mounted central processing unit into operation, a failure occurred in one central processing unit while the other central processing unit was not mounted. In this case, switching of the switching means to the side of the one central processing unit is prohibited, and the other central processing unit can be made to attempt restart processing, thereby suppressing the occurrence of a failure. be.

[Brief explanation of drawings]

Figure 1 is a configuration diagram of a conventional dual system switching control device.
FIG. 2 is a block diagram of a dual system switching control device according to an embodiment of the present invention, and FIG. 3 is a specific block diagram of the main part of FIG. 1...First CPU, 2...Second CPU, 7...
...External device, 9, 10... Signal line, 13... Connection line, 14, 15... Control interface circuit,
16, 17...control signal bus, 18...switcher,
19, 20...signal line, 21...switching control device,
22...Switching control line.

Claims (1)

[Claims] 1 Control interface circuits are connected to the buses of the first and second central processing units, respectively, and an operation/standby switching means is interposed between the control signal buses that connect each control interface circuit and external devices. The control signal bus of the external device is connected to the control interface circuit of the central processing unit on the operating side, and the switching means is normally connected to a selector circuit for signals representing the operating states of the first and second central processing units. When one of the first and second central processing units fails, the other central processing unit becomes operational, and if one central processing unit is not installed, the other central processing unit becomes operational. A dual system switching control device configured to control flip-flip by switching a selector circuit to a signal representing a mounting state when a central processing unit fails to put the mounted central processing unit into an operational state.