CN117498856B - Heterogeneous dual-mode redundancy timer, chip and vehicle - Google Patents
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Abstract
The invention discloses a heterogeneous dual-mode redundancy timer, a chip and a vehicle, wherein the timer comprises: the device comprises a clock control circuit, a main timer circuit, a heterogeneous redundancy timer circuit and a comparison circuit, wherein the main timer circuit comprises a main counter, and the heterogeneous redundancy timer circuit comprises a redundancy counter; the clock control circuit is respectively connected with the main counter and the redundant counter and is used for triggering the main counter and the redundant counter to start counting; and the comparison circuit is respectively connected with the main counter and the redundant counter, and is used for inverting the first count value of the main counter and comparing the inverted first count value with the second count value of the redundant counter, or inverting the second count value and comparing the inverted second count value with the first count value and outputting a comparison result signal to external equipment. The timer has better safety, effectively reduces the consumption of hardware resources and the participation degree of software, has smaller hardware cost and is easy to realize in circuit design.
Description
Technical Field
The invention relates to the technical field of chips, in particular to a heterogeneous dual-mode redundancy timer, a chip and a vehicle.
Background
In the field of automotive electronics, various electronic components have risks of systematic failure and random hardware failure, so that the automotive industry puts higher requirements on the safety of chips, and the functional safety design of automotive chips becomes more and more important. The dual-mode redundancy design (DMR, dual Modular Redundancy) in the chip can avoid single-point faults, improve the usability and stability of the system, and when the main module breaks down, the redundancy module can continue to work and generate error warning, so that the processing capacity and response speed of the system are improved. While the dual mode redundancy design increases the hardware cost of the system, it can increase the availability and reliability of the system, reduce downtime, risk costs, and maintenance costs, and ultimately reduce overall ownership costs. Meanwhile, compared with a redundancy design made by using the same circuit, the heterogeneous dual-mode redundancy realized by using two circuits with different structures can effectively avoid common cause failures and similar failures, and further improves the safety of modules and systems. The timer module is a circuit commonly used in a control chip, and has the main functions of timing/counting, timing control, clock generation and the like, so that the timer module is widely used in various application scenes. Therefore, the random failure rate of the timer is reduced and the system safety of the timer is improved through the dual-mode redundancy design. Compared with the common dual-mode redundancy of the same type, the dual-mode redundancy design of the timer is realized by using the heterogeneous redundancy circuit with reverse counting, so that the safety of the timer is effectively improved, and the cost overhead of software and hardware is reduced.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems in the related art to some extent. Therefore, the invention aims to provide a heterogeneous dual-mode redundant timer, a chip and a vehicle, wherein the timer has better safety, effectively reduces the consumption of hardware resources and the participation degree of software, has smaller hardware cost and is easy to realize in circuit design.
To achieve the above object, an embodiment of a first aspect of the present invention provides a heterogeneous dual-mode redundancy timer, the timer comprising: the device comprises a clock control circuit, a main timer circuit, a heterogeneous redundancy timer circuit and a comparison circuit, wherein the main timer circuit comprises a main counter, and the heterogeneous redundancy timer circuit comprises a redundancy counter; the clock control circuit is respectively connected with the main counter and the redundant counter and is used for triggering the main counter and the redundant counter to start counting; the comparison circuit is respectively connected with the main counter and the redundant counter, and is used for inverting the first count value of the main counter and comparing the inverted first count value with the second count value of the redundant counter, or inverting the second count value and comparing the inverted second count value with the first count value, and outputting a comparison result signal to external equipment.
In addition, the heterogeneous dual-mode redundancy timer of the above embodiment of the present invention may further have the following additional technical features:
according to one embodiment of the invention, the heterogeneous redundant timer circuit further comprises a first NOT gate, the timer further comprising: and the bus control circuit is connected with the main counter, is connected with the redundant counter through the first NOT gate and is used for writing a first initial value into the main counter and writing a second initial value into the redundant counter respectively, wherein the first initial value is the second initial value after being inverted.
According to one embodiment of the invention, the master timer circuit further comprises: a main period register, a main comparison register and a judgment logic unit; the bus control circuit is also respectively connected with the main period register and the main comparison register and is used for writing a first period value into the main period register and writing a first comparison value into the main comparison register; the judging logic unit is respectively connected with the main counter, the main period register and the main comparison register and is used for counting and controlling the main counter and outputting control signals to the external equipment according to the first period value, the first comparison value and the first count value.
According to one embodiment of the invention, the heterogeneous redundancy timer circuit includes: the bus control circuit is also connected with the redundancy period register and the redundancy comparison register through the first NOT gate respectively and is used for writing a second period value into the redundancy period register and writing a second comparison value into the redundancy comparison register, wherein the first period value is the second period value after being inverted, and the first comparison value is the second comparison value after being inverted; the redundancy judgment logic unit is respectively connected with the redundancy counter, the redundancy period register and the redundancy comparison register and is used for counting and controlling the redundancy counter according to the second period value, the second comparison value and the second count value.
According to an embodiment of the present invention, when the determining logic unit performs count control on the master counter, the determining logic unit is configured to control, when the first count value reaches the first period value or the first comparison value, the count mode of the master counter to switch from a current first count mode to a second count mode, where the first count mode is an inverse mode of the second count mode; and the redundancy judgment logic unit is used for controlling the counting mode of the redundancy counter to be switched from the current second counting mode to the first counting mode when the second counting value reaches the second period value or the second comparison value when the redundancy counter is subjected to counting control, and the counting mode is kept opposite to the counting mode of the main counter.
According to an embodiment of the present invention, the judging logic unit is configured to control a counting mode of the master counter when the first count value reaches the first period value or the first comparison value when the master counter is subjected to counting control; and the redundancy judgment logic unit is used for controlling the counting mode of the redundancy counter when the second count value reaches the second period value or the second comparison value when the redundancy counter is subjected to counting control.
According to one embodiment of the present invention, the judging logic unit is configured to output a module interrupt signal, a DMA request signal, or a timer output signal to the external device when the first count value reaches the first period value or the first comparison value when outputting a control signal to the external device.
According to one embodiment of the present invention, a comparison circuit includes: the input end of the second NOT gate is connected with the redundancy counter and is used for carrying out inverting operation on the second count value; the first input end of the comparator is connected with the output end of the second NOT gate, the second input end of the comparator is connected with the main counter, and the comparator is used for comparing the first count value with the inverted second count value and outputting an error signal to the synchronous unit when the first count value is inconsistent with the inverted second count value; the synchronization unit is connected with the output end of the comparator and is used for sending an error mark signal to the external equipment after synchronously sampling the error signal.
To achieve the above object, an embodiment of a second aspect of the present invention provides a chip, including: the heterogeneous dual-mode redundancy timer described above.
To achieve the above object, an embodiment of a third aspect of the present invention provides a vehicle, including: the chip described above.
The heterogeneous dual-mode redundant timer, the chip and the vehicle provided by the embodiment of the invention have the advantages of better safety, effective reduction of hardware resource consumption and software participation degree, smaller hardware expenditure and easiness in realization in circuit design.
Drawings
FIG. 1 is a block diagram of a heterogeneous dual mode redundancy timer according to one embodiment of the present invention;
FIG. 2 is a block diagram of a heterogeneous dual mode redundancy timer according to another embodiment of the present invention;
FIG. 3 is a schematic diagram of the operation state of a heterogeneous dual mode redundancy timer according to one embodiment of the present invention;
FIG. 4 is a block diagram of the structure of a chip according to one embodiment of the invention;
fig. 5 is a block diagram of a vehicle according to an embodiment of the present invention.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.
The heterogeneous dual-mode redundancy timer, the chip and the vehicle according to the embodiments of the present invention are described below with reference to the accompanying drawings.
FIG. 1 is a block diagram of a heterogeneous dual mode redundancy timer according to one embodiment of the present invention.
As shown in fig. 1, the heterogeneous dual mode redundancy timer 100 includes: a clock control circuit 101, a master timer circuit 102, a heterogeneous redundancy timer circuit 103, and a comparison circuit 104, the master timer circuit 102 including a master counter 1021, the heterogeneous redundancy timer circuit 103 including a redundancy counter 1031; the clock control circuit 101 is connected to the master counter 1021 and the redundant counter 1031, and is used for triggering the master counter 1021 and the redundant counter 1031 to start counting; the comparison circuit 104 is connected to the main counter 1021 and the redundant counter 1031, and is configured to invert the first count value of the main counter 1021, compare the inverted first count value with the second count value of the redundant counter 1031, or invert the second count value, compare the inverted second count value with the first count value, and output a comparison result signal to an external device.
Specifically, the master counter 1021 and the redundancy counter 1031 count in opposite ways to ensure heterogeneous relationships of the master timer circuit 102 and the heterogeneous redundancy timer circuit 103, such as: the master counter 1021 is one up (each beat of the count clock triggers the master counter to increment in the run state) and the redundant counter 1031 is one down (each beat of the count clock triggers the master counter to decrement in the run state).
The heterogeneous dual-mode redundant timer provided by the embodiment of the invention has better safety, effectively reduces the hardware resource consumption and the software participation degree, has smaller hardware cost and is easy to realize in circuit design.
In some embodiments, as shown in fig. 2, heterogeneous redundant timer circuit 103 further includes a first not gate 1032, heterogeneous dual mode redundant timer 100 further includes: the bus control circuit 105 is connected to the master counter 1021 and the redundancy counter 1031 through a first not gate 1032, and is configured to write a first initial value into the master counter 1021 and a second initial value into the redundancy counter 1031, respectively, where the first initial value is inverted and then is the second initial value.
Specifically, in order to achieve a convenient configuration operation, when the master counter 1021 is written, an inverted value is automatically written to the corresponding redundancy counter 1031. For example, assuming that the counter is 12 bits, an initial value 000 is written to the master counter 1021, and an initial value FFF is automatically written to the redundancy counter 1031. The write operation of the bus control circuit 105 can effectively reduce the operation times of software to the redundancy counter 1031, and save software resources.
In some embodiments, as shown in fig. 2, the master timer circuit 102 further comprises: a main cycle register 1022, a main comparison register 1023, and a judgment logic unit 1024; the bus control circuit 105 is further connected to the main period register 1022 and the main comparison register 1023, and is configured to write a first period value into the main period register 1022 and write a first comparison value into the main comparison register 1023; the judging logic unit 1024 is connected to the master counter 1021, the master period register 1022 and the master comparison register 1023, and is used for performing count control on the master counter 1021 and outputting a control signal to an external device according to the first period value, the first comparison value and the first count value.
In some embodiments, as shown in fig. 2, heterogeneous redundancy timer circuit 103 comprises: the bus control circuit 105 is further connected to the redundancy period register 1033 and the redundancy comparison register 1034 through a first not gate 1032, and is configured to write a second period value into the redundancy period register 1033 and write a second comparison value into the redundancy comparison register 1034, where the first period value is the second period value after being inverted, and the first timing stop value is the second timing stop value after being inverted; the redundancy determination logic unit 1035 is connected to the redundancy counter 1031, the redundancy period register 1033, and the redundancy comparison register 1034, and is configured to count and control the redundancy counter 1031 according to the second period value, the second comparison value, and the second count value.
Specifically, as can be seen from the above, the values written by the bus control circuit 105 into the main counter 1021 and the redundancy counter 1031 are opposite; the bus control circuit 105 writes the main comparison register 1023 and the redundancy comparison register 1034 with opposite values; the bus control circuit 105 writes the main cycle register 1022 and the redundant cycle register 1033 with opposite values; the operation times of the software to the redundancy counter 1031 can be effectively reduced by writing the opposite value through the first NOT gate 1032, and software resources are saved.
In some embodiments, the determining logic 1024 is configured to control the counting mode of the master counter 1021 to switch from the current first counting mode to the second counting mode when the first counting mode reaches the first periodic value or the first comparison value when the master counter 1021 is in counting control, wherein the first counting mode is the inverse of the second counting mode; the redundancy determination logic 1035 is configured to control the counting mode of the redundancy counter 1031 to switch from the current second counting mode to the first counting mode when the second count value reaches the second period value or the second comparison value, when the redundancy counter 1031 is controlled to count. The judging logic unit 1024 may further control the main counter 1021 to keep the counting mode unchanged when the first count value reaches the first period value or the first comparison value, and the redundancy judging logic unit 1035 may further control the redundancy counter 1031 to keep the counting mode unchanged when the second count value reaches the second period value or the second comparison value.
Specifically, when the heterogeneous dual-mode redundancy timer 100 is a timer supporting the PWM output function, the counting mode of the master counter 1021 may not be unique, and the count of the redundancy counter 1031 should be kept opposite to that of the master counter 1021 in real time. For example, the primary counter 1021 is initially up to one count, the first count value reaches the maximum period value or the first timing stop value becomes down to one count, and the redundancy counter 1031 is correspondingly up to one count from one count down to one count up.
In some embodiments, the determining logic 1024 is configured to control the counting mode of the master counter 1021 when the first count value reaches the first cycle value or the first comparison value while performing the counting control on the master counter 1021; when the redundancy determination logic 1035 performs count control on the redundancy counter 1031, it is configured to control the counting mode of the redundancy counter 1031 when the second count value reaches the minimum cycle value or the second timer stop value.
The counting modes of the master counter 1021 and the redundancy counter 1031 may include: stop counting, cycle counting, add one count, add two counts, etc.
In some embodiments, as shown in fig. 2, the determining logic 1024 is configured to output a module interrupt signal, a DMA request signal, or a timer output signal to the external device when the first count value reaches the first period value or the first comparison value when outputting the control signal to the external device.
Specifically, the redundancy decision logic 1035 may only count the redundancy counter 1031 without generating a module interrupt signal, a DMA request signal, or a timer output signal, which is advantageous in terms of hardware cost.
In some embodiments, as shown in fig. 2, the comparison circuit 104 includes: the input end of the second not gate 1041 is connected with the redundancy counter 1031, and is used for performing a negation operation on the second count value; a first input end of the comparator 1042 is connected to an output end of the second NOT gate 1041, a second input end of the comparator 1042 is connected to the master counter 1021, and is used for comparing the first count value with the inverted second count value, and outputting an error signal to the synchronization unit 1043 when the first count value is inconsistent with the inverted second count value; the synchronization unit 1043 is connected to an output terminal of the comparator 1042, and is configured to send an error flag signal to an external device after synchronously sampling the error signal.
Specifically, the counter is the core of the timer circuit, and as long as the master counter 1021 and the redundancy counter 1031 are functioning properly, the vast majority of the functions of the heterogeneous dual mode redundancy timer 100 are normal. Therefore, the safety of the timer can be effectively ensured by only comparing the counter in real time. As shown in fig. 3, taking the heterogeneous dual-mode redundancy timer 100 as an example, when the master counter 1021 generates an unexpected error value at a certain point in time, i.e., b is not equal to a+1 (the inverse value of a-1), the output of the master counter 1021 is no longer equal to the inverse value of the output of the redundancy counter 1031, and the comparison circuit 104 outputs a valid error flag signal to the system-on-chip in time. Wherein, -a represents the inverse of a. By analogy, when either register in the master timer circuit 102 or the heterogeneous redundant timer circuit 103 generates an unexpected error value, a valid error flag signal is generated as long as the correct count of the counter is affected. Meanwhile, assuming that at a certain moment, the main counter 1021 and the redundant counter 1031 are subjected to the same external interference, and the same error flip is generated, because the main counter 1021 and the redundant counter 1031 are in a counter-counting relationship, the comparison circuit 104 can still output a valid error flag, so that the safety problem possibly faced by the dual-mode redundant circuit with the same structure is avoided.
In summary, in the heterogeneous dual-mode redundancy timer according to the embodiment of the present invention, the security is improved by setting the master timer circuit and the heterogeneous redundancy timer circuit, and the dual-mode redundancy implemented through the integrated design can effectively reduce the consumption of hardware resources and the participation degree of software, and the redundant circuits involved are all designed as pure digital logic, and the hardware cost is small, so that the heterogeneous dual-mode redundancy timer is easy to implement in the circuit design.
Fig. 4 is a block diagram of the structure of a chip according to an embodiment of the invention.
As shown in fig. 4, the chip 400 includes: the heterogeneous dual mode redundancy timer 100 described above.
Fig. 5 is a block diagram of a vehicle according to an embodiment of the present invention.
As shown in fig. 5, a vehicle 500 includes: the chip 400 described above.
It is to be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present invention, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
Claims (10)
1. A heterogeneous dual mode redundancy timer, the heterogeneous dual mode redundancy timer comprising: the device comprises a clock control circuit, a main timer circuit, a heterogeneous redundancy timer circuit and a comparison circuit, wherein the main timer circuit comprises a main counter, and the heterogeneous redundancy timer circuit comprises a redundancy counter; wherein,
the clock control circuit is respectively connected with the main counter and the redundant counter and is used for triggering the main counter and the redundant counter to start counting;
the comparison circuit is respectively connected with the main counter and the redundant counter, and is used for inverting the first count value of the main counter and comparing the inverted first count value with the second count value of the redundant counter, or inverting the second count value and comparing the inverted second count value with the first count value, and outputting a comparison result signal to external equipment.
2. The heterogeneous dual redundancy timer of claim 1, wherein the heterogeneous redundancy timer circuit further comprises a first not gate, the heterogeneous dual redundancy timer further comprising:
and the bus control circuit is connected with the main counter, is connected with the redundant counter through the first NOT gate and is used for writing a first initial value into the main counter and writing a second initial value into the redundant counter respectively, wherein the first initial value is the second initial value after being inverted.
3. The heterogeneous dual redundancy timer of claim 2, wherein the master timer circuit further comprises: a main period register, a main comparison register and a judgment logic unit; wherein,
the bus control circuit is also respectively connected with the main period register and the main comparison register and is used for writing a first period value into the main period register and writing a first comparison value into the main comparison register;
the judging logic unit is respectively connected with the main counter, the main period register and the main comparison register and is used for counting and controlling the main counter and outputting control signals to the external equipment according to the first period value, the first comparison value and the first count value.
4. The heterogeneous dual-mode redundancy timer of claim 3, wherein the heterogeneous redundancy timer circuit comprises: a redundancy period register, a redundancy comparison register, and redundancy judgment logic unit, wherein,
the bus control circuit is further connected with the redundancy period register and the redundancy comparison register through the first NOT gate respectively, and is used for writing a second period value into the redundancy period register and writing a second comparison value into the redundancy comparison register, wherein the first period value is the second period value after being inverted, and the first comparison value is the second comparison value after being inverted;
the redundancy judgment logic unit is respectively connected with the redundancy counter, the redundancy period register and the redundancy comparison register and is used for counting and controlling the redundancy counter according to the second period value, the second comparison value and the second count value.
5. The heterogeneous dual-mode redundancy timer of claim 4, wherein,
the judging logic unit is configured to control, when the first count value reaches the first period value or the first comparison value, the counting mode of the master counter to switch from a current first counting mode to a second counting mode, where the first counting mode is an inverse mode of the second counting mode;
and the redundancy judgment logic unit is used for controlling the counting mode of the redundancy counter to be switched from the current second counting mode to the first counting mode when the second counting value reaches the second period value or the second comparison value when the redundancy counter is subjected to counting control, and the counting mode is kept opposite to the counting mode of the main counter.
6. The heterogeneous dual-mode redundancy timer of claim 4, wherein,
the judging logic unit is used for controlling the counting mode of the main counter when the first count value reaches the first period value or the first comparison value when the main counter is subjected to counting control;
and the redundancy judgment logic unit is used for controlling the counting mode of the redundancy counter when the second count value reaches the second period value or the second comparison value when the redundancy counter is subjected to counting control.
7. The heterogeneous dual redundancy timer of claim 5, wherein the determination logic unit is configured to output a module interrupt signal, a DMA request signal, or a timer output signal to an external device when the first count value reaches the first period value or the first comparison value when outputting a control signal to the external device.
8. The heterogeneous dual redundancy timer of claim 1, wherein the comparison circuit comprises: a second NOT gate, a comparator and a synchronization unit, wherein,
the input end of the second NOT gate is connected with the redundant counter and is used for carrying out inverting operation on the second count value;
the first input end of the comparator is connected with the output end of the second NOT gate, the second input end of the comparator is connected with the main counter, and the comparator is used for comparing the first count value with the inverted second count value and outputting an error signal to the synchronous unit when the first count value is inconsistent with the inverted second count value;
the synchronization unit is connected with the output end of the comparator and is used for sending an error mark signal to the external equipment after synchronously sampling the error signal.
9. A chip, comprising: the heterogeneous dual-mode redundancy timer of any of claims 1-8.
10. A vehicle, characterized by comprising: the chip of claim 9.
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| US7036059B1 (en) * | 2001-02-14 | 2006-04-25 | Xilinx, Inc. | Techniques for mitigating, detecting and correcting single event upset effects in systems using SRAM-based field programmable gate arrays |
| JP2006221435A (en) * | 2005-02-10 | 2006-08-24 | Oki Electric Ind Co Ltd | Memory circuit |
| KR101127038B1 (en) * | 2011-01-13 | 2012-03-26 | 두산중공업 주식회사 | System having timing synchronization function |
| DE102014112124A1 (en) * | 2013-09-06 | 2015-03-12 | Analog Devices Technology | DEVICE AND METHOD FOR EVALUATING THE PERFORMANCE OF A SYSTEM IN A CONTROL LOOP |
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