JPH06132946A - Redundant constitution device - Google Patents

Abstract

PURPOSE:To provide a redundant constitution device which can prevent a wrong switching control instruction. CONSTITUTION:An in-use circuit 100 is provided to output an input signal after applying the prescribed processing to the signal together with a stand-by circuit 200 and a switching control part 500. The circuit 100 usually performs the output operation. When the circuit 100 has a fault, the circuit 100 is switched to the circuit 200 by the switching control signal sent from the part 500 via a bus. In regard to a redundant constitution device of such a constitution, a continuous control signal deciding means 130 is added to switch the circuit 100 to the circuit 200 only when the switch control signals are continuously received twice or more at both circuits 100 and 200.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a redundant configuration device.

[0002]

2. Description of the Related Art FIG. 10 is a block diagram showing a configuration of a switching control system of an example transmission device. FIG. 11 is a block diagram showing the configuration of a conventional CPU bus interface circuit.

In FIG. 10, 1 is a block of the active system, 2
Is a spare block, and 5 is a switching controller. The CPU 6 of the switching control unit 5 performs in-device monitoring and switching control of the transmission device according to the program 7. Switching control signal is CP
It is sent from U6 to the block 1 of the active system and the block 2 of the standby system via the CPU bus and added to the CPU bus interface circuits 3-1 and 3-2, respectively.

A signal from the transmission line on the input side is divided into two by a hybrid circuit (HYB) 8 and added to blocks 1 and 2 of the active system and the standby system. Normally, in the active block 1, the switch 4-1 is turned on by the switching control signal sent from the CPU 6 via the CPU bus, and H
The signal input from YB8 is output from the active block 1 to the transmission line on the output side. At this time, the switch 4-2 of the backup system block 2 remains off.

When a circuit or the like (not shown) in the block 1 of the active system fails, the switch 4-1 of the block 1 of the active system is turned off and the switch 4-2 of the block 2 of the standby system is turned on by the switching control signal. When turned on, the signal input from the HYB 8 is output from the block 2 of the backup system to the transmission line on the output side.

FIG. 11 shows the structure of the above-mentioned CPU bus interface circuit. In FIG.
At 11, it is determined whether the addresses A _{1 to} A _n input from the CPU 6 of the switching control unit 5 via the address bus are addresses assigned to the switching control flip-flop circuit (hereinafter referred to as FF circuit) 14. . This address decoder
11 uses inversion logic, so the above address is FF
"L" level if circuit 14 applies, otherwise
Output "H" level signal.

On the other hand, in the buffer 12, data from the CPU 6
Data D sent via the bus ₁~ D_nIs the device
Whether the data is the lock data (corresponding) or not is determined by the CPU 6
From the chip select signal (C
S), and if applicable, this data
Take in.

At the same time, the pulse of the write signal (WR) sent from the CPU 6 and the address decoder 11 described above.
The output of "L" causes the logical sum circuit (hereinafter referred to as "OR circuit") 13 to output "H" at the rising timing of the pulse of the write signal (WR) and to the clock terminal (C) of the FF circuit 14. Add. Then, the data D _{1 to} D _n input from the buffer 12 are output from the FF circuit 14 at the rising timing of the pulse of the write signal.

The switching control signal determination circuit 15 determines the content of the switching signal for the data output from the FF circuit 14, and the switch 4-1 in the block 1 of the active system or the block 2 of the standby system described above. Alternatively, control the switching of switch 4-2.

[0010]

However, in the above-described circuit configuration, the bus coming from the CPU is not protected at all, and erroneous switching is caused by noise generated on the CPU bus or an accident due to runaway of the CPU. There was a problem in that

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a redundant configuration device which prevents an erroneous switching control command from being received.

[0012]

The above problems can be solved by the structure of the apparatus shown in FIG. 1 or 2. In FIG. 1, there are working and protection circuits (100 and 200) that perform predetermined processing on an input signal and output, and a switching control section 500. Normally, the working circuit 100 outputs and the working circuit 100 outputs. In the redundant configuration device in which the switching control signal sent from the switching control unit 500 via the bus when the failure occurs, and the redundant configuration device outputs from the spare circuit 200, 130 is the working circuit.
The continuous control signal determining means is provided in 100 and the spare circuit 200, and switches from the working circuit to the spare circuit only when the switching control signal is continuously received twice or more.

In FIG. 2, there are provided working and protection circuits (100 and 200) for performing a predetermined process on an input signal and outputting the same, and a switching control section 500, which is normally output from the working circuit 100 and used. When a failure occurs in the circuit 100, the redundant configuration device that switches the output by the switching control signal sent from the switching control unit 500 via the bus and outputs from the spare circuit 200,
210 is provided in the working circuit 100 and the spare circuit 200, and is provided from the working circuit only when the second switching control signal is received within a predetermined time after receiving the first switching control signal. It is a control signal determination means for switching to the spare circuit.

[0014]

In FIG. 1, for example, when a CPU provided in the switching control unit 500 runs out of control or instantaneous noise occurs on the bus, switching is performed by only one switching control signal as in the conventional case. In the case of the configuration, erroneous switching may be performed, but as in the present invention, the continuous control signal determination means 13
If the switching circuit is switched from the current circuit 100 to the spare circuit 200 only when the switching control signal is continuously received twice at 0, an erroneous switching command is not transmitted to the switching circuit.
It is possible to prevent an erroneous switching operation.

Further, in FIG. 2, the control signal judging means 210
Within 2 hours after receiving the first switching control signal at
By switching from the current circuit 100 to the spare circuit 200 only when the switching control signal for the second time is received, for example, a runaway of the CPU provided in the switching control unit 500 or a momentary noise on the bus occurs. In this case, since the wrong switching command is not transmitted to the switching circuit, the wrong switching operation can be prevented.

[0016]

1 is a block diagram showing the configuration of a CPU bus interface circuit according to a first embodiment of the first invention.

FIG. 4 is a time chart for explaining the circuit operation of FIG. FIG. 5 is a block diagram showing the configuration of the CPU bus interface circuit of the second embodiment of the first invention.

FIG. 6 is a CPU of the first embodiment of the second invention.
It is a block diagram which shows the structure of a bus interface circuit. FIG. 7 is a time chart for explaining the circuit operation of FIG.

FIG. 8 is a CPU of the second embodiment of the second invention.
It is a block diagram which shows the structure of a bus interface circuit. FIG. 9 is a time chart for explaining the circuit operation of FIG.

The same reference numerals denote the same objects throughout the drawings. In FIG. 3, the addresses A _{1 to} A _n input from the CPU 6 via the address bus in the address decoder 11 are F
When it is determined that the F circuit 14 is applicable, since the address decoder 11 employs the inversion logic, the "L" level signal is output and added to the OR circuit 13-1, and the FF circuit 17 is also provided.
To the data terminal (D) (see (1) and (2) in Fig. 4). At the same time, a buffer is sent from the CPU 6 via the control bus.
The chip select signal (CS) input to 12 also becomes "L" (see (3) in FIG. 4). When the buffer 12 receives the "L" level chip select signal (CS), the data D _{1 to} D _n input via the data bus are fetched into a circuit (not shown) in the buffer 12 ((4 in FIG. 4). )).

Thereafter, in the buffer 12, the write signal (WR) received from the CPU 6 via the control bus is ORed.
In addition to 13-1, the first write control is performed by the rising portion of the write signal pulse (see (6) in FIG. 4). At the same time, a logical product circuit (hereinafter referred to as an AND circuit) 16
The logical product of the write signal (WR) and the read signal (RD) sent from the PU 6 is obtained. However (in this case), since the read signal is at the “H” level, the write signal (WR) itself is stored in the FF circuit 17. By adding to the clock terminal (C), D at the timing of the rising part of the pulse
The "L" level signal input to the terminal is output from the Q terminal. (See (8) and (9) in Fig. 4).

Next, when the second write signal (WR) is input to the buffer 12, the FF is written by the first write.
Since the output of the circuit 17 is "L", the same signal as the rising portion of the pulse of the write signal (WR) applied to the OR circuit 13-1 is applied from the OR circuit 13-1 to the clock terminal (C) of the FF circuit 14. (See (10) and (11) in FIG. 4).

In the FF circuit 14, the clock terminal (C) input
Was input from buffer 12 and was remembered at that time
Data 3 Q₁~ Q_nOutput from the terminal. Further next (3
From the FF circuit 14 by the write signal (WR)
Data 4 Q₁~ Q_nOutput from the terminal (see (12) in Fig. 4)
See). In the switching control signal determination circuit 15, the Q of the FF circuit 14 ₁
~ Q_nJudgment based on the output from the terminal, switching control signal
To the switch 4-1 or 4-2 of its own block shown in Fig. 10.
It

As shown by the hatched lines in (1) of FIG. 4, when the address input by the address decoder 11 does not correspond to this device block, the address decoder 11 outputs an "H" level signal (see FIG. 4 (2)), since the chip select signal (CS) also becomes "H" (see (3) in FIG. 4), the buffer 12 outputs the data 5 and data 7 corresponding to the shaded portions of the address described above. not output from the output terminal Q ₁ to Q _n (see (5) in FIG. 4).

Therefore, at the timing (indicated by *) next to the first shaded portion shown in (1) of FIG. 4, the rising signal of the pulse is input from the AND circuit 16 to the clock terminal (C) of the FF circuit 17 and the first time. Even if the writing control of
At the next timing, the output of the address decoder 11 becomes "H" corresponding to the shaded area (data 7) ((1) in FIG. 4,
(See (2)), and the output of the OR circuit 13-1 remains "H" (see (11) in FIG. 4). Therefore, Q _{1 to} Q _{n of the} FF circuit 14
Data 4 is continuously output from the terminal (see (12) in FIG. 4).

Next, at the timing (indicated by *) next to the second shaded portion shown in FIG. 4A, the rising signal of the pulse from the AND circuit 16 is sent to the clock terminal (C) of the FF circuit 17. The input is newly input and the first write control is performed. At this time, the outputs of the address decoder 11 and the FF circuit 17 both become "L", so the write signal (W
R) output controls the second writing, and FF
Newly output data 9 from Q ₁ to Q _n terminal of the circuit 14 (in FIG. 4 (2), (9), (10), (11) and (12) see).

As a result, since the switching control is performed only when the switching control signal is continuously received twice from the switching control unit 5, an erroneous switching operation can be prevented even if an erroneous switching control command is received. it can.

Next, a second embodiment of the first invention shown in FIG. 5 will be described. The second embodiment differs from the first embodiment described above in that an FF circuit 18 is additionally provided in the circuit of FIG. 3, the output of the FF circuit 17 is added to the FF circuit 18, and the FF circuit 18 is added.
The output of both 17 and the FF circuit 18 is added to the OR circuit 13-2. As a result, the switching operation is not controlled by the switching control command for two consecutive times, and the switching operation is performed for the first time by the switching control command for three consecutive times.

As a result, by connecting two or three FF circuits in multiple stages and guarding at least three consecutive writes and at least four consecutive writes, momentary noise generated on the CPU bus and CPU runaway may occur. It is possible to prevent instantaneous interruption of the transmission line due to erroneous switching due to an accident.

Next, the first embodiment of the second invention will be described with reference to FIGS. 6 and 7. 6, when the address A ₁ to A _n input from CPU6 in the address decoder 11 via the address bus is determined to correspond to the FF circuit 14, the address decoder 11 by inverting the logic "L"
A level signal is output and added to the OR circuit 13-3,
It is added to the OR circuit 19 (see (1) and (2) in FIG. 7). To the OR circuit 19, a write signal (WR) sent from the CPU 6 via the buffer 12 and a Q terminal output of a monostable multivibrator 20 described later are also added.

Since the output of the Q terminal of the monostable multivibrator 20 is normally at "L" level, the output of the OR circuit 19 is "L", but the write signal (W
R) The output of the OR circuit 19 is
It becomes "H", and the rising pulse signal resets the timer composed of the monostable multivibrator 20, and the first write control is performed ((8) and (1 in Fig. 7).
(See 0)).

In the monostable multivibrator 20, the "H" level is output from the Q terminal for a fixed time determined by the resistor R and the capacitor C connected to the input side, and the inverting output terminal IN
Output "L" level signal from V Q terminal ((8) in Fig. 7,
(See (9)).

The "L" level signal of this INV Q terminal output is O
Although added to the R circuit 13-3, the address decoder described above
Since the signal applied from 11 to the OR circuit 13-3 is also at "L" level, when the second write signal (WR) is applied to the OR circuit 13-3 via the buffer 12, the pulse of this write signal rises. The FF circuit 14 is driven by the part,
The data 3 (in this case) stored in the FF circuit 14 is Q ₁ ~
Output from the _Qn terminal ((9), (10), (11) and (1
2)).

When the address input by the address decoder 11 does not correspond to this device block, as indicated by the slanted lines in (1) of FIG. 7, the address decoder 11 outputs a "H" level signal ( Since the chip select signal (CS) also becomes "H" (see (3) in Fig. 7), the data 5 and the data 7 corresponding to the shaded portion of the address described above are output from the buffer 12. Is not output from the output terminals Q _{1 to} Q _n (see (5) in FIG. 7).

Therefore, the data 5 shown in (1) of FIG.
The next timing of the corresponding shaded area (corresponding to data 6)
Then, in the rising part of the pulse of the write signal (WR)
The INV Q output of the monostable multivibrator 20 is "L".
However, it will correspond to the shaded part (data 7) at the next timing
Then, the output of the address decoder 11 becomes "H" (see FIG. 7).
See (1) and (2)), and read signal (RD) "L" level.
The bell signal is input and the write signal (WR) remains "H".
Since there are up to (6 (6) and (7) in FIG. 7), OR circuit 13-3
Output remains "H" (see (11) in Fig. 7). others
Q of FF circuit 14 ₁~ Q_nOutput data 3 from the terminal and continue
(See (12) in Fig. 7).

Next, at the timing (corresponding to data 8) next to the shaded portion corresponding to data 7 shown in (1) of FIG. 7, the monostable multivibrator 20 is driven by the rising portion of the pulse of the write signal (WR). INV Q output is "L" for a certain time
Therefore, the first write control is newly performed. At this time, since the output of the address decoder 11 also becomes "L", the write signal (WR) output of the buffer 12 performs the second write control at the next timing (corresponding to the data 9), and the Q of the FF circuit 14 is controlled. newly output data 9 from ₁ to Q _n terminals (in FIG. 7 (2), (9), (10), (11) and (12) see).

As a result, after the timer composed of the monostable multivibrator 20 is reset by the first write signal, the switching control is accepted and the switching control is performed only when the switching control signal is sent within a fixed time. By doing so, even if an erroneous switching control command is received, an erroneous switching operation can be prevented.

Next, a second embodiment of the second invention will be described with reference to FIGS. 8 and 9. The second embodiment differs from the first embodiment shown in FIG. 6 in that the monostable multivibrator shown in FIG. 8 is provided after the timer constituted by the monostable multivibrator 20 in the circuit of FIG. The timers composed of 21 are connected in cascade, and after resetting by the first write signal within the fixed time decided by the first stage timer circuit, within the fixed time decided by the second stage timer (that is, the first time The second write signal (switch control command) input when a certain time has elapsed after the write signal was input
By this, switching control is performed (see FIG. 9).
(8), (9) and (10)).

As a result, by connecting the timers in cascade, it is possible to set the acceptance time of the switching control command such as from a certain fixed time to a certain fixed time, and erroneous switching due to an accident such as noise generated on the CPU bus or CPU runaway. It is possible to prevent a momentary disconnection of the transmission line due to.

[0040]

As described above, according to the present invention, the continuous control signal determining means 130 is provided in the working circuit 100 and the spare circuit 200, and the working control signal is received only when the switching control signal is continuously received twice or more. The circuit 100 is switched to the spare circuit 200, or the control signal determination means 210 is provided in the working circuit 100 and the spare circuit 200, and the second time is received within a predetermined time after receiving the first switching control signal. By switching the current circuit 100 to the spare circuit 200 only when the switching control signal of the above is received, for example, a runaway of the CPU provided in the switching control unit 500 or a momentary change in the bus may occur. When noise occurs, an erroneous switching command is not transmitted to the switching circuit, so that an erroneous switching operation can be prevented and a momentary disconnection of the line due to erroneous switching can be prevented.

[Brief description of drawings]

FIG. 1 is a principle diagram of the invention of claim 1,

2 is a principle diagram of the invention of claim 2, FIG.

FIG. 3 is a block diagram showing a configuration of a CPU bus interface circuit of a first embodiment of the first invention,

FIG. 4 is a time chart for explaining the circuit operation of FIG.

FIG. 5 is a block diagram showing a configuration of a CPU bus interface circuit of a second embodiment of the first invention,

FIG. 6 is a block diagram showing a configuration of a CPU bus interface circuit of a first embodiment of the second invention,

FIG. 7 is a time chart for explaining the circuit operation of FIG.

FIG. 8 is a block diagram showing a configuration of a CPU bus interface circuit of a second embodiment of the second invention,

9 is a time chart for explaining the circuit operation of FIG.

FIG. 10 is a block diagram showing a configuration of a switching control system of an example transmission device,

FIG. 11 is a block diagram showing a configuration of a conventional CPU bus interface circuit.

[Explanation of symbols]

100 is a current circuit, 130 is a continuous control signal determination means, 200
Is a spare circuit, 210 is a control signal determination means, and 500 is a switching control unit.

Claims (2)

[Claims] 1. A working control circuit (100 and 200) for performing a predetermined process on an input signal and outputting the same, and a switching control section (5).
00), which is normally output from the working circuit (100) and is switched by the switching control signal sent from the switching control unit (500) via the bus when the working circuit (100) fails. In the redundant configuration device for performing the output from the spare circuit (200), the working circuit (100) and the spare circuit (200) receive the switching control signal continuously two or more times only,
A redundant configuration device comprising a continuous control signal determination means (130) for switching from the working circuit to the spare circuit. 2. A working control circuit (100 and 200) for performing a predetermined process on an input signal and outputting the processed signal and a switching control section (5).
00), which is normally output from the working circuit (100) and is switched by the switching control signal sent from the switching control unit (500) via the bus when the working circuit (100) fails. In the redundant configuration device that performs the output from the spare circuit (200), the working circuit (100) and the spare circuit (200) receive the second switching control signal within a predetermined time after receiving the first switching control signal. A redundant configuration device comprising a control signal determining means (210) for switching from the working circuit to the spare circuit only when the switching control signal is received for the first time.