JPS644221B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a multiprocessor in which communication between each processor is configured by a common bus.

Conventional structure and its problems Traditionally, the duplex synchronization processing method for multiprocessors takes the duplex processor system as one element and combines this element with multiple processors. The configuration was not such that output was sent to each of the two processors of the element independently. FIG. 1 shows an example of the conventional multiprocessor duplex synchronization processing method shown in FIG. In Figure 1, CBUS is a common bus, CP ₁ , CP ₁ ′, CP ₂ , CP ₂ ′, ... CPn, CPn′ are processors, MPIF ₁ , MPIF ₂ , ..., MPIFn
are common bus interfaces, PE ₁ , PE ₂ , ...
PEn is a terminal device, PEIF ₁ , PEIF ₂ , ... PEIFn is a terminal interface, and L ₁ , L ₂ , ..., Ln is a line for fault monitoring. In the multiprocessor shown in Fig. 1, for example, in a redundant processor system element consisting of processor CP ₁ and processor CP ₁ ', processor CP ₁ is operated as the main system and processor CP ₁ ' is operated as the slave system. Then, the input data coming via the common bus CBUS is received by the common bus interface MPIF ₁ , transferred simultaneously to the master processor CP ₁ and the slave processor CP ₁ ', and then transferred to the common bus interface MPIF 1.
The data output to CBUS is sent to the main processor CP ₁ using the common bus interface MPIF ₁ .
The output data of is selected and output. terminal device
For input/output between PE ₁ , main processor CP ₁ , and slave processor CP ₁ ', the terminal device
Input data from PE ₁ is sent to the terminal interface.
Received by PEIF ₁ , main processor CP ₁
Output data of the main processor CP ₁ is selected by the terminal interface PEIF ₁ and outputted from the data that is simultaneously transferred to the slave processor CP _{1 '} and output to the terminal device PE ₁ .

In such conventional multiprocessors, the configuration of the common bus CBUS, the common bus interfaces MPIF ₁ , MPIF ₂ ,
..., MPIFn configuration, terminal interface
The configuration of PEIF ₁ , PEIF ₂ , ..., PEIFn is determined,
Common bus interface MPIF ₁ , MPIF ₂ ,...,
MPIFn and terminal interface PEIF ₁ ,
Since PEIF ₂ ,...,PEIFn are configured to perform synchronous verification processing, each must have a synchronous verification circuit, making the device complex and large. It was not possible to run it as a single processor, and the multiprocessor as a whole had a configuration with little flexibility.

OBJECTS OF THE INVENTION It is an object of the present invention to eliminate the disadvantages of the conventional redundant synchronization processing of multiprocessors and to provide a multiprocessor that can perform duplex synchronization processing with great flexibility with a simple system configuration. It is in.

Structure of the Invention In order to achieve the above object, the present invention connects the first and second processors to a common bus, connects them by a synchronization verification bus, and connects the first and second processors to either the first or second processor. A switching means is provided to switch the connection with the terminal device,
Further, the first and second processors and the terminal device are coupled to the first common bus, and the first and second processors are coupled by a synchronization verification bus, so that either the first or second processor A switching means is provided for switching the connection between one and the second common bus.

DESCRIPTION OF EMBODIMENTS Examples of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the multiprocessor of the present invention. In the figure,
CBUS is a common bus, CP ₁ , CP ₁ ′, CP ₂ , CP ₂ ′...
CPn, CPn′ are processors, SBUS ₁ , SBUS ₂ ,...
..., SBUSn is the synchronous verification bus, SW ₁ , SW ₂ , ...
SWn indicates a changeover switch, and PE ₁ , PE ₂ , ... PEn indicate a terminal device. Each processor CP ₁ , CP ₁ ′, CP ₂ ,
CP ₂ ′, . . . CPn, CPn′ are each directly connected to the common bus CBUS. Furthermore, the connections between the processors CP ₁ , CP ₁ ′, CP ₂ , CP ₂ ′, ... CPn, CPn' and the terminal devices PE ₁ , PE ₂ , ... PEn are provided by changeover switches SW ₁ , SW ₂ , ...PEn, respectively. ...Achieved by SWn.

Now, in the multiprocessor shown in Fig. 2, for example, in a redundant processor system element consisting of processor CP ₁ and processor CP ₁ ', processor CP ₁ is designated as the main system and
When CP ₁ ′ is operated as a slave, the common bus CBUS
Input data coming through is simultaneously taken into the main and slave processors CP ₁ and CP ₁ ', and the same processing is performed by each processor CP ₁ and CP ₁ '. On the other hand, assuming that the terminal device DE ₁ is always connected only to the main processor CP ₁ by the changeover switch SW ₁ , the input data from the terminal device PE ₁ is taken in only to the main processor CP ₁ . Therefore, the main processor CP ₁ is the terminal device
The input data from PE ₁ is transferred to the slave processor CP ₁ ' via the common bus CBUS, and the same processing is performed by the master and slave processors CP ₁ and CP ₁ '.

The results of the same processing are determined by the synchronous matching programs of the main and slave processors CP ₁ and CP ₁ ′.
The data is transferred from the conventional processor CP ₁ ' to the main processor CP ₁ via the synchronous verification bus SBUS ₁ , and the main processor CP ₁ performs synchronous verification processing, and the results of the same processing are shared between the main and slave processors. The processors CP ₁ and CP ₁ ' of the system determine whether or not they are equal. If they are not equal, the processors CP ₁ and CP ₁ ' of the main system and the slave system perform fault processing.

For example, the main processor CP ₁ determines that the slave processor CP ₁ ' is at fault, and sends the common bus to the slave processor CP ₁ '.
A failure report is sent via CBUS, and the main processor is then used as a single processor.
Processing continues only on CP ₁ , and the slave processor
When CP ₁ ' receives a fault report from main processor CP ₁ via the common bus CBUS, it may start an internal diagnostic program and perform self-diagnosis.

If the results of the same processing are the same, only the main processor CP ₁ performs the output processing and outputs the results of the same processing. In this way, multiprocessor duplication synchronization processing is executed.

By the way, depending on the function, you may want to run each redundant processor as a single processor.
Alternatively, there may be times when a failure occurs in the main processor CP ₁ , and in such cases, the conventional processor CP ₁ ' can switch the changeover switch SW ₁ under program control to restore the conventional processor.
By operating CP ₁ ′ as an independent processor, the main and slave processors CP ₁ ,
It is possible to operate each CP ₁ ′ as a single processor, and it is also possible to operate only the slave processor CP ₁ ′.

In this way, according to this embodiment, the main and slave processors CP ₁ and CP ₁ ' are connected to each other by a synchronous verification bus, and an interface having a conventional synchronous verification circuit is connected to the common bus CBUS. Since they are connected without going through the interface, the equipment is simplified, and both processors
Since CP ₁ and CP ₁ ' can each be operated as a single unit, it is possible to configure a multiprocessor that can perform duplex synchronization processing with great flexibility as a whole.

FIG. 3 is a block diagram showing another embodiment of the multiprocessor of the present invention. In the figure,
CBUS ₁ is a common bus to which changeover switches SW ₁ , SW ₂ , ...SWn are connected, and CBUS ₂ is a common bus connected to processors CP ₁ , SWn.
CP ₁ ', CP ₂ , CP ₂ '...CPn, CPn' are directly connected to a common bus, and terminal devices PE ₁ , PE ₂ ...PEn are connected to the common bus CBUS ₂ . SBUS ₁ ,
_SBUS2 ...SBUSn are synchronization verification buses similar to the embodiment shown in FIG.

When the multiprocessor shown in Fig. 3 is operated with processor CP ₁ as the main system and processor CP ₁ ' as the slave system, the input data from the terminal device PE ₁ is as follows.
The data is simultaneously taken into the main and slave processors CP ₁ and CP ₁ ' via the common bus CBUS ₂ , and the same processing is performed by each processor CP ₁ and CP ₁ '. On the other hand, the common bus CBUS ₁ is a changeover switch.
Assuming that SW ₁ is always connected only to the main processor CP ₁ , input data coming via the common bus CBUS ₁ will be sent to the main processor CP 1.
_{The main processor CP 1 transfers} the input data from the common bus CBUS ₁ to the slave processor CP ₁ ' via the common bus CBUS ₂ , and The slave processors CP ₁ and CP ₁ ' perform the same processing. The result of the same processing is the master and slave processors CP ₁ ,
Under the control of the synchronous verification program of CP ₁ ′, the data is transferred from the slave processor CP ₁ ′ to the master processor CP ₁ via the synchronous verification bus SBUS ₁ , and
The main processor CP ₁ performs synchronous verification processing. As a result of synchronous verification processing, the slave processor
If CP ₁ ′ is determined to be at fault, a fault notification is sent to the slave processor CP ₁ ′ via the common bus CBUS ₂ , and from then on, the main processor CP ₁
operates as a single processor. If it is determined that there is no abnormality as a result of the synchronization verification, only the main processor CP ₁ outputs the same processing result. In this way, multiprocessor duplication synchronization processing is executed.

When operating the main and slave processors CP ₁ and CP ₁ ′ as single units, the changeover switch is controlled by the conventional processor CP ₁ ′.
SW ₁ can be switched to perform the same operation as in the previous embodiment.

In this way, since this embodiment also includes the synchronization verification bus SBUS ₁ and the changeover switch SW ₁ , a multiprocessor with a simple configuration, flexibility, and ability to perform duplex synchronization processing can be obtained.

Effects of the Invention As explained above, the present invention provides the first and second
processors are coupled by a synchronization bus, each processor is coupled to a common bus, and a terminal device is coupled to the first and second processors via a switch, or a terminal device is coupled to the common bus. The synchronous verification process is performed by the synchronous verification programs of the first and second processors to connect the synchronous verification bus and other common buses to the first and second processors via a changeover switch. This eliminates the need for a redundant interface with a complicated synchronization matching circuit as in the past, simplifying the overall configuration of the device, and allowing each processor to be configured according to its function. A multiprocessor capable of performing redundant synchronous processing can be obtained, which can be operated as a single processor, thereby increasing the flexibility of the entire device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional multiprocessor, FIG. 2 is a block diagram showing one embodiment of the multiprocessor of the present invention, and FIG. 3 is a block diagram showing another embodiment of the present invention. It is. CBUS, CBUS ₁ , CBUS ₂ ...Common bus, CP ₁ ,
CP ₁ ′, CP ₂ , CP ₂ ′ to CPn, CPn′...processor, PE ₁ , PE ₂ to PEn... terminal device, SBUS ₁ ,
SBUS ₂ , ~SBUSn...Synchronization verification bus, SW ₁ ,
SW ₂ , ~SWn...changeover switch.

Claims (1)

[Scope of Claims] 1. First and second processors connected to a common bus, a synchronous verification bus that connects the first and second processors to perform synchronous verification, and It has a terminal device controlled by a processor, and switching means for coupling the terminal device to either the first or second processor, and normally the terminal device is connected to the first processor by the switching means. or a multiprocessor connected to either one of the second processors and configured such that data input from the terminal device is transferred from one processor to the other processor via the common bus. 2 a first and a second bus coupled to the first common bus;
a terminal device connected to the first common bus and controlled by the first or second processor; and a synchronous verification bus that connects the first and second processors to perform synchronous verification. , switching means for coupling either the first or second processor to a second common bus, and normally the second common bus is connected to the first or second processor by the switching means. a multiprocessor connected to either one of the processors, and configured such that data input from the second common bus is transferred from one processor to the other processor via the first common bus. Sir.