JPS5919497A - Digital time division exchange - Google Patents

Digital time division exchange

Info

Publication number
JPS5919497A
JPS5919497A JP12936182A JP12936182A JPS5919497A JP S5919497 A JPS5919497 A JP S5919497A JP 12936182 A JP12936182 A JP 12936182A JP 12936182 A JP12936182 A JP 12936182A JP S5919497 A JPS5919497 A JP S5919497A
Authority
JP
Japan
Prior art keywords
switch
output
input
diagnostic
common use
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12936182A
Other languages
Japanese (ja)
Inventor
Takeshi Nishiyama
西山　竹志
Keitaro Sakurai
桜井　恵太郎
Toshio Kobori
小堀　敏雄
Hirotaka Sasaki
佐々木　寛隆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP12936182A priority Critical patent/JPS5919497A/en
Publication of JPS5919497A publication Critical patent/JPS5919497A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

PURPOSE:To improve the reliability of a system, by connecting alternatly plural common use/spare time switches to a diagnostic control circuit sequentially for attaining usually the diagnosis without stopping the exchange operation. CONSTITUTION:A signal on plural channels from an input highway (HW) 2 is connected for exchange to any of common use time switches 1a-1m via a gate circuit 7, and outputted to an output HW3 via a gate circuit 8. A diagnosis control circuit 4 including a pattern generator and a collating circuit for diagnosis is connected sequentially to the common use time switches 1a-1m and the spare time switch 1n via input and output buses 5, 6 and the gate circuits 7, 8 for diagnosing the time switches. While one of the common use time switches is connected to the diagnosis control circuit 4, the spare time switch 1n performs the exchange connection of signals in place of the common use switch.

Description

【発明の詳細な説明】 本発明は、ディジタル時分割交換機に関するもので、交
換機の運転中にも通話路網の診断を可能２べ′−；゛ にし、常に通話路の正常動作を維持することを目的とす
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital time-division switching system, and is capable of diagnosing a communication path network even while the switching system is in operation, thereby maintaining normal operation of the communication path at all times. With the goal.

従来の交換機においては、第１図のような構成が用いら
れてきた。In conventional exchanges, a configuration as shown in FIG. 1 has been used.

第１図のＳ、、Ｓ２．・・・・・ＳＮは常用タイム・ス
イッチ＋　ＳＮ＋１は予備タイム・スイッチである。S, , S2 in FIG. ...SN is a regular time switch + SN+1 is a backup time switch.

ＨＷ−１，ＨＷ−２は、常用タイム・スイッチＳ１゜Ｓ
２．・・・・・・ＳＮが異常の時予備タイム・スイッチ
ＳＮ＋１に切換えるためのゲートである。HW-1 and HW-2 are regular time switches S1°S
2. ...This is a gate for switching to the standby time switch SN+1 when SN is abnormal.

上記構成で、時分割信号がゲートＧ−１を経由して入力
すると、常用タイム・スイッチＳ１．Ｓ２・・・・・Ｓ
Ｎを制御系（図示せず）でオン・オフすることにより通
話路を交換接続し、その出力はゲートＧ−２を経由して
出力ハイウェイＨＷ−２に出力する。もし前記常用タイ
ム・スイッチＳ１．Ｓ２．、。In the above configuration, when a time division signal is input via gate G-1, common time switch S1. S2...S
N is turned on and off by a control system (not shown) to exchange and connect communication paths, and its output is output to output highway HW-2 via gate G-2. If the regular time switch S1. S2. ,.

・・・ＳＮのいずれもが故障した時は、故障したタイム
スインチに代えて、予備タイム・スイッチＳＮ＋１を用
いていた。しかしこの構成によると常用系に異常が生じ
た時に予備系に切換えを可能にしたに過ぎない。このた
め故障診断のために運転を中止３′：−ミ′ する必要があわ、不便であった。...When any of the SNs failed, the backup time switch SN+1 was used in place of the failed time switch. However, this configuration merely makes it possible to switch to the standby system when an abnormality occurs in the regular system. For this reason, it was necessary to stop operation for fault diagnosis, which was inconvenient.

本発明は上記した従来の欠点を除去したもので、以下そ
の一実施例により図面と共に説明する。第２図において
、１ａ、１ｂ・・・・・・１ｍは常用タイム・スイッチ
群を示し、１ｎは予備タイム・スイッチである。２は通
話信号の入力用ノ・イウエイ、３は通話信号の出力用ノ
・イウエイ、４は診断のだめのパターンジェネレータ、
照合回路を有する診断制御回路、５，６は診断制御回路
４から出る診断信号の入出力バスである。７，８はそれ
ぞれ診断のためタイム・スイッチ（群）１ａ・・・・・
・１ｎを入出力ハイウェイ２，３に接続し、更に常用及
び予備タイム・スイッチ１ａ・・・・・・１ｎで走査し
、入出力バス５，６を順次接続するゲート回路である。The present invention eliminates the above-mentioned conventional drawbacks, and will be described below with reference to an embodiment thereof with reference to the drawings. In FIG. 2, 1a, 1b, . . . 1m represent a group of regular time switches, and 1n is a backup time switch. 2 is a wire for inputting a call signal, 3 is a wire for outputting a call signal, 4 is a pattern generator for diagnosis,
A diagnostic control circuit having a verification circuit, 5 and 6 are input/output buses for diagnostic signals output from the diagnostic control circuit 4. 7 and 8 are time switches (group) 1a for diagnosis respectively.
1n is connected to the input/output highways 2 and 3, and further scanned by the regular and standby time switches 1a...1n, and is a gate circuit that sequentially connects the input/output buses 5 and 6.

次にこの実施例の動作を説明する。入カッ・イウェイ２
より入力された複数チャンネルの信号は、常用タイム・
スイッチｉａ、１ｂ・・・・・・１ｍのいずれかにより
制御部（図示せず）のコントロールの下で交換接続され
て、同じく複数チャンネルの出力信号として出カッ・イ
ウエイ３に出力される。Next, the operation of this embodiment will be explained. Entering Kawaiiway 2
Multi-channel signals input from
The signals are exchanged and connected under the control of a control unit (not shown) using any of the switches ia, 1b, .

ところで、診断用信号を送る入力バスと入カッ・イウェ
イ２とがゲート７により常用・予備タイム・スイッチ１
ａ、１ｂ・・・・・１ｎに切換接続される。By the way, the input bus that sends diagnostic signals and the input time switch 2 are connected to the regular/standby time switch 1 by the gate 7.
A, 1b...1n are switched and connected.

また常用・予備タイム・スイッチ１ａ、１ｂ・・・・・
・１ｎはゲート８により出カッ・イウエイ３と出力バス
６へ切換接続される。このようにして入出力ゲー）７．
８は常用タイム・スイッチ１ａ、１ｂ・・・・・・１ｍ
の１つを順次走査して入出力バス５，６に接続し、その
間は切換えられたタイム・スイッチの代りに予備タイム
・スイッチＳ−７−６、が常用タイム・スイッチとして
接続され通常動作を行う。Also, regular use/standby time switches 1a, 1b...
・1n is switched and connected to the output way 3 and the output bus 6 by the gate 8. In this way, the input/output game)7.
8 is the regular time switch 1a, 1b...1m
one of them is sequentially scanned and connected to input/output buses 5 and 6, and during that time, a standby time switch S-7-6 is connected as a regular time switch in place of the switched time switch, and normal operation is performed. conduct.

一方入出力バスフ、８に対しては、診断制御回路４が接
続され、診断用信号パターンを発生し入力バス５に送る
。On the other hand, a diagnostic control circuit 4 is connected to the input/output bus 8, which generates a diagnostic signal pattern and sends it to the input bus 5.

被診断タイム・スイッチを経て出力されるパターンを出
力バス６から受取り、送出パターンと照合してタイム・
スイッチの正常動作が診断される。The pattern output via the time switch to be diagnosed is received from the output bus 6, compared with the sent pattern, and the time
The normal operation of the switch is diagnosed.

この動作を各常用タイム・スイッチ１ａ、１ｂ・・・・
・・１ｍについて行い順次運転動作中の診断故障発見を
行う。This operation is performed on each regular time switch 1a, 1b...
・・Perform for 1m and sequentially perform diagnostic fault detection during operation.

５ページ 以上説明したように本発明によれば、交換動作を中止す
ることなく常時診断を行うことが出来るので、システム
の信頼性を高めることを可能にする利点を有する。As explained on page 5 and above, according to the present invention, diagnosis can be performed at all times without interrupting the replacement operation, so it has the advantage of increasing the reliability of the system.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、従来のディジタル時分割交換機のブロック図
、第２図は本発明の一実施例によるディジタル時分割交
換機のブロック図である。 １ａ〜１ｍ・・・・・・常用タイム・スイッチ、１ｎ・
・・・・・予備タイム・スイッチ、２・・・・・・入カ
ッ翫イウエイ、３・・・・・・出カッ・イウエイ、４・
・・・・・診断制御回路、５・・・・・・入力ハス、６
・・・・・・出力ハス、７，８・・・・・・ケート回路
。 代理人の氏名　弁理士　中　尾　敏　男　ほか１名第１
図 ｌFIG. 1 is a block diagram of a conventional digital time division switch, and FIG. 2 is a block diagram of a digital time division switch according to an embodiment of the present invention. 1a~1m...Common time switch, 1n.
...Preliminary time switch, 2...Input signal, 3...Output signal, 4.
...Diagnostic control circuit, 5...Input lotus, 6
...Output lotus, 7, 8... Kate circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure l

Claims (1)

【特許請求の範囲】[Claims] 通話路の時分割による交換接続を行う常用タイム・スイ
ッチおよび予備タイム・スイッチと、複数チャンネルの
ティジタル信号が入力されると、同ディジタル信号が出
力される出力ハイウェイと診断入力バスと、診断出力バ
スと、前記入力ハイウェイと診断入力バスを前記常用、
予備タイム・スイッチに切替接続する入力ゲートと、前
記出力ハイウェイと前記診断カバスを前記諧用、予備タ
イム・スイッチに切換接続する出力ゲートと、前記診断
入力バスに診断信号を送り、前記診断出力バスからの出
力を受けてスイッチの動作を診断する診断制御回路とを
備えたディジタル時分割交換機。A regular time switch and a standby time switch that perform time-division switching connections for communication paths, an output highway to which digital signals from multiple channels are output when the same digital signals are input, a diagnostic input bus, and a diagnostic output bus. and using the input highway and the diagnostic input bus,
an input gate for switching connection to the backup time switch; an output gate for switching connection of the output highway and the diagnostic bus to the harmonization and backup time switch; A digital time division switch equipped with a diagnostic control circuit that diagnoses the operation of the switch by receiving output from the switch.
JP12936182A 1982-07-23 1982-07-23 Digital time division exchange Pending JPS5919497A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12936182A JPS5919497A (en) 1982-07-23 1982-07-23 Digital time division exchange

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12936182A JPS5919497A (en) 1982-07-23 1982-07-23 Digital time division exchange

Publications (1)

Publication Number Publication Date
JPS5919497A true JPS5919497A (en) 1984-01-31

Family

ID=15007683

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12936182A Pending JPS5919497A (en) 1982-07-23 1982-07-23 Digital time division exchange

Country Status (1)

Country Link
JP (1) JPS5919497A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6257327A (en) * 1985-09-05 1987-03-13 Oki Electric Ind Co Ltd Line setting circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6257327A (en) * 1985-09-05 1987-03-13 Oki Electric Ind Co Ltd Line setting circuit

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