JPS63227234A - Bus fault detecting and diagnosing circuit - Google Patents

Abstract

PURPOSE:To continue a service to a terminal equipment in which no fault is generated, by separating all of the terminal equipments from a common bus automatically when the fault is generated in the terminal equipment or the common bus, and performing the check of each terminal equipment and the common bus automatically. CONSTITUTION:When the fault is generated in either terminal equipment, a bus fault detecting means 160 detects the fault, and adds a control signal on a test means 110 provided at each terminal equipment, the contacts 90 and 100 of a switch, the contact 140 of the switch connected to the common bus 105, and a test pattern generating means 150. When the control signal being received, the contacts 90 and 100 of the switch are switched from signal sides to test sides, and as a result, each terminal is separated from the common bus 105. The test means 110 checks coincidence/discrepancy between a received pattern signal and a delivery signal, then, the detection and the diagnosis of the fault for each terminal and the common bus 105 are performed automatically. In such a way, it is possible to continue the service for the terminal in which no fault is generated.

Description

[Detailed Description of the Invention] [Summary] In a system in which a plurality of terminal devices are connected to a common bus and signals are exchanged between terminal rooms, when a failure occurs in the terminal device or the common bus, all the terminal devices By automatically disconnecting the terminal device from the common bus and automatically checking each terminal device and the common bus, it is possible to automatically and quickly diagnose the location of the fault, and to check whether the terminal device is free of faults. This allows services to continue to be provided.

[Industrial application field]

The present invention relates to a bus failure detection/diagnosis circuit in a system in which a plurality of terminal devices are connected to a common bus and signals are exchanged between the terminal devices.

In a system that uses a common bus, detection and detection of failure points is necessary to prevent a failure in one terminal device from having a ripple effect on the entire system and leaving other terminal devices unable to receive communication services. It is desirable that the diagnosis be performed quickly and that communications can continue with terminal devices that have not experienced any failures.

[Conventional technology]

FIG. 3 is a block diagram showing the configuration of a conventional common bus communication system.

In FIG. 3, for example, there are eight terminal devices 2-
1 to 2-8 are connected to the common bus 1, eight terminal devices 6-1 to 6-8 are connected to the common bus 5 on the receiving side, and these common buses 1.5 are connected to the control device 4. ing. The common bus 1.5 can be used by only one terminal device at a time on both the sending and receiving sides, and is used in a time-sharing manner.

For example, the transmitting side terminal device 2-1 and the receiving side terminal device 6
-8. First, a control signal for starting a signal is transferred from the terminal device 2-1 to the control device 4 via the common bus 1. The control device 4 sends the inquiry signal as to whether or not reception is possible to all terminal devices 6-1 on the receiving side.
~ Send to 6-8. Terminal device 6- with which you wish to communicate on the receiving side
8, if the reception is OK, a signal to that effect is sent to the control device 4.
send to The control device 4 receives this signal and sends a transmission OK signal to the transmitting terminal device 2-1. At this time, the control device 4 has confirmed that both the common buses 1 and 5 are free and usable. In the transmitting side terminal device 2-1,
Upon receiving the above signal, communication with the terminal device 6-8 is started.

For example, suppose that a failure occurs in the terminal device 2-5 on the transmitting side. At this time, the output of the terminal device 2-5 may have a value close to the ground potential, and since the outputs of each terminal device are connected to each other through a common bus, the terminal device 6-5 on the receiving side
In this case, it becomes impossible to accurately receive the signal from the terminal device 2-1.

For this reason, each terminal device 2-1 to 2-8 and 6-1 to 6
-8 to detect the fault location. To do this, manually disconnect each terminal device 2-1 to 2-8 and 6-1 to 6-8 from the common bus 1 and 5, and then Tests were conducted to detect failure points.

[Problem that the invention seeks to solve]

However, the conventional method described above has the problem that when a failure occurs in a terminal device, all terminal devices connected to the common bus cannot receive service, and it takes time to recover.

[Means for solving problems]

The above problem is solved by the bus interface section 3 which receives input signals and matches the signals to the common bus, as shown in FIG.
0-1 and whose outputs are connected to the common bus 80-1 to 80-n, and the common bus 1 that transmits the signals.
05, bus failure detection means 160 detects a failure when a failure occurs in the bus interface unit 30-1 or the common bus 105 and outputs a control signal, and the bus interface unit 30-1. and the input terminal 170, and the bus interface section 30-1
and the common bus 105, the switch contacts 90 and 100 have the function of switching from the signal side to the test side in response to a control signal, and the switch contacts 90. When the received signal is received via the bus interface unit 30-1 and the switch contact 00, and the predetermined pattern output signal matches the received signal, the switch contacts 90 and 100 are switched to the signal side, and when they do not match, the switch is switched to the signal side. A test means 110 that outputs a control signal to hold the contacts 90 to 100 on the test side, and a switch contact 140 that is connected to the common bus 105 and turns on/off in response to a control signal from the bus fault detection means 160. and a test pattern generating means 150 that outputs a predetermined pattern of signals according to a control signal, and the output of the test pattern generating means 150 is
This problem is solved by the bus failure detection/diagnosis circuit of the present invention in which the bus failure detection means 160 checks via the switch contacts 140 and the common bus 105.

[Effect]

In FIG. 1, when a failure occurs in any of the terminal devices, the bus failure detection means 160 detects it as a continuous "0#" signal, for example, and sends a control signal to the test means 110 provided in each terminal device, and the contact point of the switch. 90.100, the contact 140 of the switch connected to the common bus 105, and the test pattern generating means 150.

Contacts 90 and 100 of the switch receive this control signal and switch from the signal side to the test side. As a result, each terminal device is disconnected from the common bus 105.

Also, the contact 140 of the switch is switched from off to on.

At the same time, a predetermined pulse pattern signal is sent from the test means 110 and received by the test means 110 via the switch contacts 90, the bus interface section 30-1, and the switch contacts 100.

The test means 110 checks whether the received pattern signal matches the transmitted signal.

- If it fails, it is determined that no failure has occurred in this terminal device, and the control signal is sent to the switch contact 90.1.
0 and return the switch to the signal side.

If they do not match, it is determined that a failure has occurred in this terminal device, and the contacts 90 and 100 of the switch are left on the test side. Then, only which terminal device is disconnected from the common bus 105 to repair the faulty part.

On the other hand, in response to the control signal applied from the bus failure detection means 160, the test pattern generation means 150 sends out a predetermined pattern of signals, which are transferred to the bus failure detection means 160 via the switch contacts 140 and the common bus 105. .

The received pattern signal is checked by the pattern check means included in the bus failure detection means 160, and the presence or absence of a failure on the common bus is investigated in the same manner as described above.

In this way, failures in each terminal device and the common bus can be automatically detected and diagnosed.

〔Example〕

FIG. 2 is a block diagram showing the configuration of a bus failure detection/diagnosis circuit according to an embodiment of the present invention.

The same reference numerals indicate the same objects throughout the figures.

In FIG. 2, each terminal device and the common bus indicate the transmitting side.

For example, assume that a failure occurs in one of the eight terminal devices 8-1 to 8-8 or in the common bus 1.

A counter (not shown) included in the bus failure detection unit 16
etc., this is detected as a continuous “0” signal,
Control signals are applied to the switch contacts 9,10 and to the fixed memory device (hereinafter referred to as ROM) 12.

At the switch contacts 9.10, a control signal switches the switch contacts to the test side.

At the same time, a control signal is applied from the ROM 12 to the test pattern generating section 11, and the test pattern generating section 11 outputs a pattern signal of a predetermined pulse. This pulse pattern signal is transmitted to the switch contact 9 and the bus interface section 3.
-1 and is applied to the pattern check section 13 via the switch contact 0.

The pattern check section 13 is composed of, for example, a known error detector that checks the error rate of a pulse signal, and checks whether the input signal matches the output signal of the test pattern generation section 11. If they match, it is determined that no fault has occurred in this terminal device, and a signal (for example, "1") indicating this is added to the ROM 12. In response to this, the ROM 12 adds a control signal to switch contacts 9 and 10 to return them to the original signal side.
Reconnect the switch contacts.

Furthermore, when the received signal does not match the output signal of the test pattern generating section 11, the pattern checking section 13 determines that a fault has occurred in this terminal device, and leaves the contacts 9 and 10 of the switch as they are. In other words, with this terminal device disconnected from the common bus 1, repair work for the faulty part is performed.

Next, as a result of diagnosing all the terminal devices using the above method, when it is found that no fault has occurred in any of the terminal devices, the bus fault detection section 16 sends the switch contact 14,
and a control signal is applied to the test pattern generating section 15. Then, the contact 14 of the switch is turned on, and the test pattern generator 15 outputs a predetermined pulse pattern signal, which is applied to the bus fault detection unit 16 via the switch contact 14 and the common bus 1. . A pattern check unit (not shown) included in the bus failure detection unit 16
In this way, it is determined whether or not a failure has occurred in the common bus 1 in the same manner as the above method.

〔Effect of the invention〕

As described above, according to the present invention, when a failure occurs in a terminal device or a common bus, the failure location can be automatically and quickly detected and diagnosed.

Further, by automatically disconnecting only the terminal device in which a fault has occurred from the common bus, it is possible to continue service to terminal devices in which no fault has occurred.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention. FIG. 2 is a block diagram showing the configuration of a bus failure detection/diagnosis circuit according to an embodiment of the present invention. FIG. 3 is a block diagram showing the configuration of a conventional common bus communication system. It is. In the figure, 30-1 is a bus interface section, 80-1, . 80-n is a terminal device, 90.100.140 is a switch contact, 105 is a common bus, 110 is a test means, 150 is a test pattern generation means, and 160 is a bus failure detection means.

Claims (1)

[Scope of Claims] A bus interface section (30-1) that receives an input signal and matches the signal to a common bus, and the terminal device (80-1 to 80-80) whose output is connected to the common bus. -n) and a common bus (105) for transmitting the signal, when a failure occurs in the bus interface unit (30-1) or the common bus (105), between a bus fault detection means (160) that detects and outputs a control signal, and the bus interface section (30-1) and the input terminal (170);
and the bus interface section (30-1) and the common bus (1
05), and has the function of switching from the signal side to the test side by the control signal (90
) and (100), outputting a signal of a predetermined pattern according to the control signal,
The contact point (90) of the switch, the bus interface part (3
0-1) and a switch contact (100), and when the output signal of the predetermined pattern and the received signal match, the switch contacts (90) and (100) are switched to the signal side; If they do not match, the contact point (9) of the switch
0), (100) on the test side, and the common bus (100).
5), a switch contact (140) that is turned on/off by a control signal from the bus failure detection means (160), and a test pattern generation means that outputs a predetermined pattern of signals according to the control signal. (150), and the output of the test pattern generation means (150) is checked by the bus failure detection means (160) via the switch contacts (140) and the common bus (105). bus fault detection and diagnostic circuit.