JPS59134804U - Sequence calculation circuit in sequence control device - Google Patents

Sequence calculation circuit in sequence control device

Info

Publication number
JPS59134804U
JPS59134804U JP2526083U JP2526083U JPS59134804U JP S59134804 U JPS59134804 U JP S59134804U JP 2526083 U JP2526083 U JP 2526083U JP 2526083 U JP2526083 U JP 2526083U JP S59134804 U JPS59134804 U JP S59134804U
Authority
JP
Japan
Prior art keywords
sequence
control device
calculation circuit
sequence control
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2526083U
Other languages
Japanese (ja)
Inventor
岩井　文雄
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP2526083U priority Critical patent/JPS59134804U/en
Publication of JPS59134804U publication Critical patent/JPS59134804U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの考案の一実施例であるシーケンス制御装置
におけるシーケンス−算回路の回路構成を示すブロック
図、第２図は第１図のシーケンス演算回路を備えたシー
ケン不制御装置の回路構成を示すブロック図、第３図は
第２図のシーケンス制御装置に適用されるＭＯＶ命令を
示す構成図である。 図において、１・・・命令デコーダ、２・・・演算器、
３・・・演算結果保持レジスタ、４・・・ＡＮＢ、ＯＲ
Ｂスタック、５・・・マスクコントローラ、６・・・演
算データ選択マルチプレクサ、７・・・データ保持レジ
スタ、８・・・データスワップマルチプレクサ、９・・
・タイミングジェネレータ、１１・・・中央処理装置（
ＣＰＵ）、１２・・・クロックジェネレータ、１３・・
・バスコントローラ、１４・・・アドレスラッチ、１５
・・・アドレスデコーダ、１６・・・ｌ１０（入出力）
インタフェース、１７・・・メモリ、１８・・・シーケ
ンス演算回路、１９゜２０・・・相方向性バッファであ
る。なお、図中、同一符号は同一、又は相当部分を示す
。FIG. 1 is a block diagram showing the circuit configuration of a sequence calculation circuit in a sequence control device that is an embodiment of this invention, and FIG. 2 shows the circuit configuration of a sequence non-control device equipped with the sequence calculation circuit of FIG. 1. The block diagram shown in FIG. 3 is a configuration diagram showing the MOV command applied to the sequence control device of FIG. 2. In the figure, 1... instruction decoder, 2... arithmetic unit,
3...Arithmetic result holding register, 4...ANB, OR
B stack, 5... mask controller, 6... calculation data selection multiplexer, 7... data holding register, 8... data swap multiplexer, 9...
・Timing generator, 11...Central processing unit (
CPU), 12...Clock generator, 13...
・Bus controller, 14...Address latch, 15
...Address decoder, 16...l10 (input/output)
Interface, 17...Memory, 18...Sequence calculation circuit, 19°20... Phase directional buffer. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] マイクロプロセッサシステムによるシーケンス制御装置
において、シーケンス制御に必要なシーケンス命令の演
算、データ処理を、中央処理装置とは独立して、ハード
ウェアで行なうようにした回路から成る構成としたシー
ケンス制御装置におけるシーケンス演算回路。In a sequence control device using a microprocessor system, a sequence in a sequence control device configured with a circuit in which the calculation of sequence instructions and data processing necessary for sequence control are performed by hardware, independent of the central processing unit. Arithmetic circuit.
JP2526083U 1983-02-23 1983-02-23 Sequence calculation circuit in sequence control device Pending JPS59134804U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2526083U JPS59134804U (en) 1983-02-23 1983-02-23 Sequence calculation circuit in sequence control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2526083U JPS59134804U (en) 1983-02-23 1983-02-23 Sequence calculation circuit in sequence control device

Publications (1)

Publication Number Publication Date
JPS59134804U true JPS59134804U (en) 1984-09-08

Family

ID=30156250

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2526083U Pending JPS59134804U (en) 1983-02-23 1983-02-23 Sequence calculation circuit in sequence control device

Country Status (1)

Country Link
JP (1) JPS59134804U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6455602A (en) * 1987-08-26 1989-03-02 Matsushita Electric Works Ltd Instruction processing circuit for programmable controller
JPH02137002A (en) * 1988-11-18 1990-05-25 Hitachi Ltd High speed sequence arithmetic processing unit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5268340A (en) * 1975-12-05 1977-06-07 Hitachi Ltd Data processing unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5268340A (en) * 1975-12-05 1977-06-07 Hitachi Ltd Data processing unit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6455602A (en) * 1987-08-26 1989-03-02 Matsushita Electric Works Ltd Instruction processing circuit for programmable controller
JPH02137002A (en) * 1988-11-18 1990-05-25 Hitachi Ltd High speed sequence arithmetic processing unit

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