JPS58150140U - arithmetic processing unit - Google Patents
arithmetic processing unitInfo
- Publication number
- JPS58150140U JPS58150140U JP4471782U JP4471782U JPS58150140U JP S58150140 U JPS58150140 U JP S58150140U JP 4471782 U JP4471782 U JP 4471782U JP 4471782 U JP4471782 U JP 4471782U JP S58150140 U JPS58150140 U JP S58150140U
- Authority
- JP
- Japan
- Prior art keywords
- arithmetic processing
- processing unit
- registers
- register
- instruction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Executing Machine-Instructions (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は処理装置の命令語の形式図、第２図は演算プロ
グラムの例示図、第３図は従来技術による目的プログラ
ムを示す図、第４図は本考案による目的プログラムを示
す図、第５図は本考案における処理装置演算部のブロッ
ク図、第６図はレジスタ格納制御図、第７図はレジスタ
格納制御部の詳細回路図である。
１・・・浮動小数点レジスタ（ＦＲ）、２・・・主記憶
装置（ＭＳ）、３・・・命令レジスタ、４・・・複数レ
ジスタ、格納制御ビット、５・・・レジスタ格納制御部
、６・・・演算部、７・・・演算器出力レジスタ、３２
〜３６・・・ＦＲ２〜ＦＲ５格納指示原信号、４０〜４
４・・・ＦＲＱ〜ＦＲ４同時格納制御ビット、５０〜５
６・・・ＦＲＱ〜ＦＲ５格納指示信号、３０１，３０２
・・・ＦＲ番号指定ビット、５゛０１・・・ＦＲ格納許
可信号。FIG. 1 is a format diagram of command words of a processing device, FIG. 2 is an exemplary diagram of an arithmetic program, FIG. 3 is a diagram showing an object program according to the prior art, FIG. 4 is a diagram showing an object program according to the present invention, and FIG. FIG. 5 is a block diagram of the processing unit calculation section of the present invention, FIG. 6 is a register storage control diagram, and FIG. 7 is a detailed circuit diagram of the register storage control section. DESCRIPTION OF SYMBOLS 1...Floating point register (FR), 2...Main memory (MS), 3...Instruction register, 4...Multiple registers, storage control bit, 5...Register storage control unit, 6 ... Arithmetic unit, 7... Arithmetic unit output register, 32
~36...FR2~FR5 storage instruction source signal, 40~4
4...FRQ to FR4 simultaneous storage control bits, 50 to 5
6...FRQ to FR5 storage instruction signal, 301, 302
...FR number designation bit, 5゛01...FR storage permission signal.
Claims (1)
ている位置の情報と、演算の種類とを命令で指定される
ことにより演算を遂行する演算処理装置において、演算
結果を格納するための個々のレジスタに対応した制御フ
リップフロップ群と、専用命令により該制御フリップフ
ロップの値を設定する機構と、該制御フリップフロップ
の値がセット状態である場合にはレジスタ番号が１多い
隣のレジスタにも同時にレジスタ書込み信号を送出する
制御機構とを具備し、演算命令で指定する格納レジスタ
が単一であるにもかかわらず、制御フリップフロップの
値によって連続する２以上の複数のレジスタに同時結果
書込みを可能とすることを特徴とする演算処理装置。An arithmetic processing unit that performs an operation by specifying information on the location of the operand, information on the location of the operand, and type of operation in an instruction, and stores the result of the operation. a group of control flip-flops corresponding to individual registers for the purpose of It is equipped with a control mechanism that simultaneously sends a register write signal to all registers, and even though a single storage register is specified by an operation instruction, it can be sent to two or more consecutive registers depending on the value of the control flip-flop. An arithmetic processing device characterized by being able to write results simultaneously.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4471782U JPS58150140U (en) | 1982-03-31 | 1982-03-31 | arithmetic processing unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4471782U JPS58150140U (en) | 1982-03-31 | 1982-03-31 | arithmetic processing unit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58150140U true JPS58150140U (en) | 1983-10-07 |
Family
ID=30055765
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4471782U Pending JPS58150140U (en) | 1982-03-31 | 1982-03-31 | arithmetic processing unit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58150140U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62119640A (en) * | 1985-11-20 | 1987-05-30 | Fujitsu Ltd | Machine language instruction pre-processing system |
-
1982
- 1982-03-31 JP JP4471782U patent/JPS58150140U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62119640A (en) * | 1985-11-20 | 1987-05-30 | Fujitsu Ltd | Machine language instruction pre-processing system |
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