JPS6181351U - - Google Patents
Info
- Publication number
- JPS6181351U JPS6181351U JP16572984U JP16572984U JPS6181351U JP S6181351 U JPS6181351 U JP S6181351U JP 16572984 U JP16572984 U JP 16572984U JP 16572984 U JP16572984 U JP 16572984U JP S6181351 U JPS6181351 U JP S6181351U
- Authority
- JP
- Japan
- Prior art keywords
- microprogram
- processing program
- auxiliary memory
- trace information
- outputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Debugging And Monitoring (AREA)
- Digital Computer Display Output (AREA)
Description
第１図より第６図は全て本考案の処理装置の一
実施例を示し、第１図は全体構成図、第２図はジ
ヨブ処理サイクルの流れ図、第３図、第４図、第
６図はそれぞれ第２図のブロツク番号３０，５０
，６０の詳細流れ図、第５図は第４図のブロツク
番号６０の詳細流れ図である。
１…主メモリ、２…データトレースフラグメモ
リ、３…セグメント番号メモリ、７…一時メモリ
、８…バツフアメモリ、９…処理装置、１３…補
助メモリ、１４…出力装置、１５…処理プログラ
ム、１６…プログラムカウンタ、１７…汎用レジ
スタ。
Figures 1 to 6 all show one embodiment of the processing apparatus of the present invention, with Figure 1 being an overall configuration diagram, Figure 2 being a flowchart of the job processing cycle, Figures 3, 4, and 6. are block numbers 30 and 50 in Figure 2, respectively.
, 60. FIG. 5 is a detailed flow chart of block number 60 in FIG. DESCRIPTION OF SYMBOLS 1... Main memory, 2... Data trace flag memory, 3... Segment number memory, 7... Temporary memory, 8... Buffer memory, 9... Processing device, 13... Auxiliary memory, 14... Output device, 15... Processing program, 16... Program Counter, 17...General-purpose register.
Claims (1)
階でデータトレース指示アドレスをとり込むマイ
クロプログラムＡと、該当アドレスに主メモリア
クセスがあれば補動メモリにトレース情報を出力
するマイクロプログラムＢ、および処理プログラ
ム終了割込み段階で、補助メモリ内のトレース情
報を出力装置に出力するマイクロプログラムＣを
設けたことを特徴とする処理装置。 In an electronic computer, a microprogram A takes in a data trace instruction address at the start stage of a processing program, a microprogram B outputs trace information to an auxiliary memory when a main memory access is made to the corresponding address, and a processing program end interrupt stage A processing device characterized in that it is provided with a microprogram C that outputs trace information in an auxiliary memory to an output device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16572984U JPS6181351U (en) | 1984-11-02 | 1984-11-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16572984U JPS6181351U (en) | 1984-11-02 | 1984-11-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6181351U true JPS6181351U (en) | 1986-05-30 |
Family
ID=30723569
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16572984U Pending JPS6181351U (en) | 1984-11-02 | 1984-11-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6181351U (en) |
-
1984
- 1984-11-02 JP JP16572984U patent/JPS6181351U/ja active Pending
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