JPS6418349U - - Google Patents

Info

Publication number
JPS6418349U
JPS6418349U JP11133987U JP11133987U JPS6418349U JP S6418349 U JPS6418349 U JP S6418349U JP 11133987 U JP11133987 U JP 11133987U JP 11133987 U JP11133987 U JP 11133987U JP S6418349 U JPS6418349 U JP S6418349U
Authority
JP
Japan
Prior art keywords
address unit
flag
computer
unit change
processing device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11133987U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11133987U priority Critical patent/JPS6418349U/ja
Publication of JPS6418349U publication Critical patent/JPS6418349U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例の処理装置全体構成
図、第2図はジヨブ処理サイクルの流れ図、第3
図は第2図のブロツク番号30の一部の詳細流れ
図である。 1……制御部、2……デコーダ、3……プログ
ラムカウンタ、4……命令レジスタ、5……バス
、6……状態レジスタ、7……演算ユニツト、8
……汎用レジスタ、9……アドレスレジスタ、1
0……データレジスタ、11……アドレス単位変
更指示フラグ、12……アドレス単位変更器、1
3……主メモリ。
Fig. 1 is an overall configuration diagram of a processing device according to an embodiment of the present invention, Fig. 2 is a flow chart of a job processing cycle, and Fig. 3 is a flow chart of a job processing cycle.
The figure is a detailed flowchart of a portion of block number 30 of FIG. DESCRIPTION OF SYMBOLS 1... Control part, 2... Decoder, 3... Program counter, 4... Instruction register, 5... Bus, 6... Status register, 7... Arithmetic unit, 8
...General-purpose register, 9...Address register, 1
0...Data register, 11...Address unit change instruction flag, 12...Address unit changer, 1
3...Main memory.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] プログラム内蔵方式の計算機において、該計算
機固有のアドレス単位と異なるアドレス単位に変
更することを指示するフラグと、該フラグをセツ
ト・リセツトするような処理を設け、さらに、ア
ドレス単位変更指示フラグがセツトされると、同
一ジヨブまたは同一タスク内の全命令に対するア
ドレス単位変更を実施するようなアドレス単位変
更器を設けたことを特徴とする処理装置。
In a built-in program computer, a flag is provided to instruct the address unit to be changed to a different address unit from that unique to the computer, and a process for setting and resetting the flag is provided, and an address unit change instruction flag is also set. 1. A processing device comprising an address unit changer that performs address unit change for all instructions within the same job or the same task.
JP11133987U 1987-07-22 1987-07-22 Pending JPS6418349U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11133987U JPS6418349U (en) 1987-07-22 1987-07-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11133987U JPS6418349U (en) 1987-07-22 1987-07-22

Publications (1)

Publication Number Publication Date
JPS6418349U true JPS6418349U (en) 1989-01-30

Family

ID=31349295

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11133987U Pending JPS6418349U (en) 1987-07-22 1987-07-22

Country Status (1)

Country Link
JP (1) JPS6418349U (en)

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