JPH03104233U - - Google Patents

Info

Publication number
JPH03104233U
JPH03104233U JP1990011290U JP1129090U JPH03104233U JP H03104233 U JPH03104233 U JP H03104233U JP 1990011290 U JP1990011290 U JP 1990011290U JP 1129090 U JP1129090 U JP 1129090U JP H03104233 U JPH03104233 U JP H03104233U
Authority
JP
Japan
Prior art keywords
program rom
interrupt vector
processing
contents
rom
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990011290U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990011290U priority Critical patent/JPH03104233U/ja
Publication of JPH03104233U publication Critical patent/JPH03104233U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の第一の実施例を示すマイクロ
プロセツサのブロツク図、第2図は本考案の第二
の実施例を示すマイクロプロセツサのブロツク図
である。 1……レジスタ、2……データバス、3……割
込みベクタ・テーブル(ROM)、4……プログ
ラム(ROM)、5……割込みコントローラ、6
……バス・コントローラ、7……命令キユー、8
……マイクロコード、9……テンポラリレジスタ
、10……ALU、11……アドレスモデイフア
イア(ADM)、12……アドレスバス、13…
…データ(RAM)、14……タイマ、15……
DMAコントローラ、16……シリアルコントロ
ーラ。
FIG. 1 is a block diagram of a microprocessor showing a first embodiment of the present invention, and FIG. 2 is a block diagram of a microprocessor showing a second embodiment of the present invention. 1...Register, 2...Data bus, 3...Interrupt vector table (ROM), 4...Program (ROM), 5...Interrupt controller, 6
...Bus controller, 7...Instruction queue, 8
... Microcode, 9 ... Temporary register, 10 ... ALU, 11 ... Address modifier (ADM), 12 ... Address bus, 13 ...
...Data (RAM), 14...Timer, 15...
DMA controller, 16... serial controller.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] CPUと割込みベクタ・テーブルROMおよび
プログラムROMとを有し、割込み処理を行なう
際に前記割込みベクタから処理アドレスを読み込
んで処理ルーチンを決定し、プログラムROMを
実行することはできても割込みベクタの内容およ
びプログラムROMの内容をデータとして読み出
すことができないようにしたことを特徴とするマ
イクロプロセツサ。
It has a CPU, an interrupt vector table ROM, and a program ROM, and when performing interrupt processing, it reads the processing address from the interrupt vector, determines the processing routine, and executes the program ROM, but the contents of the interrupt vector and a microprocessor characterized in that the contents of the program ROM cannot be read out as data.
JP1990011290U 1990-02-06 1990-02-06 Pending JPH03104233U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990011290U JPH03104233U (en) 1990-02-06 1990-02-06

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990011290U JPH03104233U (en) 1990-02-06 1990-02-06

Publications (1)

Publication Number Publication Date
JPH03104233U true JPH03104233U (en) 1991-10-29

Family

ID=31744730

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990011290U Pending JPH03104233U (en) 1990-02-06 1990-02-06

Country Status (1)

Country Link
JP (1) JPH03104233U (en)

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