JPS6452004U - - Google Patents

Description

[Brief explanation of the drawing]

1 and 2 are block diagrams of a sequence instruction processing circuit of a program controller according to an embodiment of this invention, FIG. 3 is a circuit diagram showing an example of an AND operation sequence program, and FIG. 4 is an AN
FIG. 5 is a circuit diagram showing an example of a sequence program for an OR operation, FIG. 6 is a diagram for explaining an OR operation combination, and FIG. 7 is a block diagram of a sequence instruction processing circuit of a conventional program controller. In the figure, 1 is a CPU, 2 and 4 are memories for input information, 3 is a memory for temporarily saving calculation results, 5 is a memory for storing calculation results, 6 is a sequence instruction storage memory, and 7 is a sequence instruction execution determination circuit. . In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Scope of utility model registration request] A plurality of memories that store input information, a CPU (central processing unit) that performs arithmetic processing based on the input information in this memory, a memory that temporarily stores the calculation results of this CPU, and a memory that stores the calculation results that become output information. The sequence instruction processing circuit of the programmable controller, which consists of a memory that executes programmed sequence instructions, executes or does not execute this sequence instruction depending on the type of the sequence instruction and the calculation results up to the previous step. A sequence instruction processing circuit for a programmable controller, comprising a sequence instruction execution determining means for determining whether or not the sequence instruction is executed.