JPH02281349A - Microcomputer - Google Patents

Microcomputer

Info

Publication number
JPH02281349A
JPH02281349A JP10372489A JP10372489A JPH02281349A JP H02281349 A JPH02281349 A JP H02281349A JP 10372489 A JP10372489 A JP 10372489A JP 10372489 A JP10372489 A JP 10372489A JP H02281349 A JPH02281349 A JP H02281349A
Authority
JP
Japan
Prior art keywords
memory
register
registers
contents
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10372489A
Other languages
Japanese (ja)
Inventor
Hidekazu Suda
英一 須田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP10372489A priority Critical patent/JPH02281349A/en
Publication of JPH02281349A publication Critical patent/JPH02281349A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To give a function to execute the inter-memory operation with one instruction by providing an arithmetic processing device and reading in contents of plural temporary registers and storing operation results in index registers. CONSTITUTION:An arithmetic instruction is fetched, and contents of a memory M(X) 9 addressed by an index register X1 are stored in a temporary register A6 through a data bus 5. Next, contents of a memory M(Y) 10 addressed by an index register Y2 are stored in a temporary register B7 through the data bus. Contents of registers A6 and B7 are read into an arithmetic processing device ALU 6. The operation result is stored in the memory M(X) 9 through the bus 5. Thus, the operation between memories M(X) 9 and M(Y) 10 addressed by two registers X1 and Y2 is performed with one instruction, and the result is stored in a memory RAM 4.

Description

【発明の詳細な説明】[Detailed description of the invention]

[産業上の利用分野] 本発明は、2つの記憶装置番地指示レジスタを有し、1
命令実行のみで2つの記憶装置間の演算を実行する機能
を有するマイクロコンビエータに関するものである。 〔従来の技術〕 従来のマイクロコンピュータは、データメモリのアドレ
スを指示する番地指示レジスタを1つしか持たず、2つ
のメモリ間の演算を行なうために、−度、番地指示レジ
スタを用いて一方のメモリ内容を汎用レジスタに読出し
、次に番地指示レジスタを書換えて他方のメモリを指示
し、汎用レジスタと他方のメモリとの間で演算を実行し
ていた。 〔発明が解決しようとする課題] しかし、従来技術では、2つのメモリ間の演算を行なう
ために、−度汎用レジスタを介する必要があり、汎用レ
ジスタの内容が保存されない、そのため、汎用レジスタ
の内容を必要に応じて退避しなければならず、プログラ
ムの容量、実行時間共効率低下が生じる。又、汎用レジ
スタの内容退避が必要ない場合も、一方のメモリ内容を
汎用レジスタに格納するプログラムが必ず必要となるた
めプログラムの容量・実行時間の効率が低下する問題点
を有する。 そこで本発明は、これらの問題点を解決するもので、そ
の目的とするところは、2つのメモリ間の演算処理を、
2つの番地指示レジスタを用いて、又汎用レジスタを用
い、ることなく、l命令で実行する機能を提供すること
にある。 〔課題を解決するための手段] 本発明のマイクロコンビエータは、 (a)記憶装置の番地指示レジスタを、2つ又はそれ以
上有し、 (b)2つの該番地指示レジスタを用いて、2つの記憶
装置の内容を読出し、演算し、演算結果を、どちらか一
方の該番地指示レジスタによって指示される記憶装置に
書込むことを、1命令実行中に処理する機能を有するこ
とを特徴とする。 〔作 用] 本発明の上記の構成によれば、2つのメモリ間の演算処
理を、他の汎用レジスタを介することなく、2つの番地
指定レジスタを用いてl命令で、実行することができ、
プログラム容量、及び、プログラム実行時間を短縮する
ことができる。
[Industrial Application Field] The present invention has two storage device address instruction registers, one
The present invention relates to a microcombiator that has a function of executing operations between two storage devices only by executing instructions. [Prior Art] Conventional microcomputers have only one address register that specifies the address of a data memory, and in order to perform an operation between two memories, the address register is used to read one of the memories. The contents of the memory were read into a general-purpose register, then the address instruction register was rewritten to point to the other memory, and an operation was executed between the general-purpose register and the other memory. [Problems to be Solved by the Invention] However, in the conventional technology, in order to perform an operation between two memories, it is necessary to go through a general-purpose register, and the contents of the general-purpose register are not saved. must be saved as necessary, resulting in a decrease in program capacity and execution time efficiency. Further, even if it is not necessary to save the contents of the general-purpose register, a program is always required to store the contents of one memory in the general-purpose register, so there is a problem that the efficiency of the program in terms of capacity and execution time decreases. The present invention aims to solve these problems, and its purpose is to perform arithmetic processing between two memories.
The object of the present invention is to provide a function that can be executed with an instruction using two address registers and without using a general-purpose register. [Means for Solving the Problems] The microcombinator of the present invention (a) has two or more address instruction registers of a storage device, (b) uses two address instruction registers to The present invention is characterized by having a function of reading the contents of two storage devices, performing an operation, and writing the operation result to the storage device specified by one of the address instruction registers during the execution of one instruction. . [Function] According to the above configuration of the present invention, arithmetic processing between two memories can be executed with an instruction using two address specification registers without going through other general-purpose registers.
Program capacity and program execution time can be reduced.

【実 施 例】【Example】

以下に、本発明についての実施例に基づいて、詳細に説
明する。 第1図に、本発明の実施例である番地指示レジスタを2
つ持ち、1命令でメモリ間演算が可能なマイクロコンピ
ュータのフロック図を示す。 インデックス・レジスタ・X(1)、インデックス・レ
ジスタ・Y(2)が、記憶装置であるRAM (4)の
番地指示レジスタで、アドレス・バス(3)を介して、
それぞれ別のRAMアドレスを指示することができる。 インデックス・レジスタ・x(1)でアドレスでアドレ
ス指示されるメモリM(X)(9)と、インデックス・
レジスタ・Y(2)でアドレス指示されるメモリM(Y
)(10)との間で、演算を行ない、その演算結果をメ
モリM(X)(9)へ格納する場合の1命令内での処理
は以下の通りである。 まず、演算命令をフェッチし、次にインデックス・レジ
スタ・X (1)でアドレス指示されるメモリM(X)
(9)の内容を、データ・バス(5)を介してテンポラ
リ・レジスタ・A(6)へ格納する0次にインデックス
・レジスタ・Y(2)でアドレス指示さ、れるメモリM
 (Y)(10)の内容を、データ・バス(5)を介し
てテンポラリ・レジスタ・B(7)へ格納する。その後
、テンポラリ・レジスタ・A(6)とテンポラリ・レジ
スタB(7)の内容を、演算処理装置ALU (8)に
読込み、その演算結果を、データ・バス(5)を介して
、インデックス・レジスタ・X(1)をアドレス指示さ
れるメモリM(X)(9)に格納する。 以上により、l命令の中で、2つのインデックス・レジ
スタを用いて、それぞれアドレス指示されるメモリ間の
演算を行ない、その結果をメモリに格納することが可能
となる。 【発明の効果1 本発明のマイクロコンピュータは、上述のように、プロ
グラムl命令で、他の汎用レジスタな介することなく%
2つのメモリ間の演算処理を行なうことができるため、
プログラム容量、及び、プログラム実行時間を短縮する
ことができ、より効率の高いシステム制御を行なえる利
点を有する。
The present invention will be described in detail below based on examples. FIG. 1 shows two address instruction registers according to an embodiment of the present invention.
This is a block diagram of a microcomputer that can perform inter-memory operations with one instruction. Index register X (1) and index register Y (2) are address instruction registers of RAM (4), which is a storage device, and are
Each can specify a different RAM address. The memory M(X) (9) whose address is specified by the index register x(1) and the index register
Memory M(Y) whose address is specified by register Y(2)
)(10) and the result of the operation is stored in the memory M(X)(9), the processing within one instruction is as follows. First, an arithmetic instruction is fetched, and then the memory M(X) whose address is specified by the index register
The contents of (9) are stored in temporary register A (6) via data bus (5). Memory M is addressed by zero-order index register Y (2).
(Y) Store the contents of (10) into temporary register B (7) via data bus (5). After that, the contents of temporary register A (6) and temporary register B (7) are read into the arithmetic processing unit ALU (8), and the result of the operation is transferred to the index register via the data bus (5). - Store X(1) in the addressed memory M(X)(9). As described above, it becomes possible to use the two index registers in the l instruction to perform operations between the memories respectively addressed, and to store the results in the memories. Effects of the Invention 1 As mentioned above, the microcomputer of the present invention can perform % processing using program instructions without using other general-purpose registers.
Because it is possible to perform calculations between two memories,
This has the advantage that the program capacity and program execution time can be shortened, and more efficient system control can be performed.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明のマイクロコンピュータの実施例を示
すブロック図。 インデックス・レジスタ・X インデックス・レジスタ・Y アドレス・バス AM データ・バス テンポラリ・レジスタ・A テンポラリ・レジスタ・B LU M (X) M (Y)
FIG. 1 is a block diagram showing an embodiment of a microcomputer according to the present invention. Index register X Index register Y Address bus AM Data bus Temporary register A Temporary register B LU M (X) M (Y)

Claims (1)

【特許請求の範囲】 (a)記憶装置の番地指示レジスタを、2つ又はそれ以
上有し、 (b)2つの該番地指示レジスタを用いて、2つの記憶
装置の内容を読出し、演算し、演算結果を、どちらか一
方の該番地指示レジスタによって指示される記憶装置に
書込むことを、1命令実行中に処理する機能を有するこ
とを特徴とするマイクロコンピュータ。
Scope of Claims: (a) having two or more storage device address instruction registers; (b) using the two address instruction registers to read and operate the contents of two storage devices; A microcomputer characterized by having a function of writing an operation result to a storage device indicated by one of the address instruction registers during execution of one instruction.
JP10372489A 1989-04-24 1989-04-24 Microcomputer Pending JPH02281349A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10372489A JPH02281349A (en) 1989-04-24 1989-04-24 Microcomputer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10372489A JPH02281349A (en) 1989-04-24 1989-04-24 Microcomputer

Publications (1)

Publication Number Publication Date
JPH02281349A true JPH02281349A (en) 1990-11-19

Family

ID=14361619

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10372489A Pending JPH02281349A (en) 1989-04-24 1989-04-24 Microcomputer

Country Status (1)

Country Link
JP (1) JPH02281349A (en)

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