JPH0330103U

JPH0330103U -

Info

Publication number: JPH0330103U
Application number: JP8831589U
Authority: JP
Priority date: 1989-07-27
Filing date: 1989-07-27
Publication date: 1991-03-25

Description

[Brief explanation of the drawing]

第１図〜第４図はこの考案の一実施例によるプ
ラグラマコントローラを示し、第１図はＨ／Ｗ構
成図、第２図はユーザプログラムメモリとシーケ
ンスプログラムを示す図、第３図はデバイスメモ
リ構成図、第４図はＳ／Ｗフローチヤート、第５
図〜第１０図は従来のプログラマブルコントロー
ラを示し、第５図はＨ／Ｗ構成図、第６図はユー
ザプログラムメモリとシーケンスプログラムを示
す図、第７図はデバイスメモリ構成図、第８図は
演算命令を示す図、第９図は演算命令の動作図、
第１０図はＳ／Ｗフローチヤートである。図において、１はユーザプログラムメモリ、２
はＣＰＵ、３はシステムプログラムメモリ、４は
内部バス、５は入出力メモリ、６はデータメモリ
、７はフアイルメモリ、８は通信インターフエイ
ス、９はプログラミング装置である。なお、図中
、同一符号は同一、又は相当部分を示す。 1 to 4 show a programmer controller according to an embodiment of this invention, FIG. 1 is a H/W configuration diagram, FIG. 2 is a diagram showing a user program memory and a sequence program, and FIG. 3 is a device memory. Configuration diagram, Figure 4 is S/W flowchart, Figure 5
10 to 10 show a conventional programmable controller, FIG. 5 is a H/W configuration diagram, FIG. 6 is a diagram showing a user program memory and sequence program, FIG. 7 is a device memory configuration diagram, and FIG. 8 is a diagram showing a device memory configuration. A diagram showing the calculation instructions, FIG. 9 is an operation diagram of the calculation instructions,
FIG. 10 is a S/W flowchart. In the figure, 1 is a user program memory, 2 is a user program memory;
3 is a system program memory, 4 is an internal bus, 5 is an input/output memory, 6 is a data memory, 7 is a file memory, 8 is a communication interface, and 9 is a programming device. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims

[Scope of utility model registration request]

A program memory that stores user sequence programs, an input/output memory that stores the states of input/output signals to be controlled, and a data memory and file memory that mainly store input data for calculations and data of calculation results (hereinafter referred to as The three memories other than the above program memory are collectively referred to as the device memory.), and each instruction in the above program memory is executed sequentially, arithmetic processing is performed based on the data in the above device memory, and the result of the operation is used as the device memory. In a programmable controller equipped with an instruction execution means that repeatedly rewrites the contents, an instruction for performing the above calculation is used as an instruction to read data from the device memory, an instruction to perform an operation on the read data, and an instruction to transfer the data of the operation result to the device. A programmable controller characterized by being configured with instructions written to memory.