JPS647347U - - Google Patents

Description

[Brief explanation of the drawing]

Fig. 1 is an embodiment of the present invention in which the microprogram control method is applied to the board control circuit section, Fig. 2 is a general explanatory diagram of the microprogram method, Fig. 3 is a block diagram of the microprogram address sequencer, FIG. 4 is a diagram showing a typical example of microprogram instructions, and FIG. 5 is an operation flow diagram of the DRAM with ECC. 1... Control bus, 2... Address data bus, 3... Bus control circuit, 4... Board control circuit, 5... Memory control circuit, 6... Memory cell, 7... Data control circuit, 8... Data buffer circuit, 9...Memory board.

Claims (1)

[Scope of utility model registration request] A main memory device connected to a microcomputer that stores a microprogram address sequencer that generates control memory addresses based on various conditions and microinstructions that specify the control contents and microprogram operations instructed by the address sequencer. In a control device consisting of a pipeline register that prevents microprogram racing by latching the control memory and control memory output, and a control output that controls the operation of the main memory device using the register output, operation commands from the system bus are processed. 1. A main memory device using a microprogram control method, which is characterized in that it executes operations determined by the above in accordance with each condition.