JPS63168545U - - Google Patents
Info
- Publication number
- JPS63168545U JPS63168545U JP6200887U JP6200887U JPS63168545U JP S63168545 U JPS63168545 U JP S63168545U JP 6200887 U JP6200887 U JP 6200887U JP 6200887 U JP6200887 U JP 6200887U JP S63168545 U JPS63168545 U JP S63168545U
- Authority
- JP
- Japan
- Prior art keywords
- program
- memory
- storage means
- test
- debugged
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 238000013507 mapping Methods 0.000 description 1
Landscapes
- Debugging And Monitoring (AREA)
Description
第１図は本考案の構成説明図、第２図は本考案
の実施例のハードウエア構成例を示すブロツク図
および、第３図はテストプログラムの内容例を示
す流れ図である。
図において、１…バス、２…マイクロプロセツ
サ（ＭＰＵ）、３…ＲＯＭ、４…ＲＡＭ、５…メ
モリマツプ化Ｉ／Ｏ用ＲＡＭ、６…入力インタフ
エイス、７…出力インタフエイス、８…補助記憶
制御回路、９…入力器、１０…出力器、１１…補
助記憶装置、２０…被デバツグプログラムの格納
手段、２１…メモリマツプ化Ｉ／Ｏ用のメモリ、
２２…テストプログラムの格納手段、２３…出力
手段、２４…実行手段、ＤＰ…被デバツグプログ
ラム、ＴＰ…テストプログラム。
FIG. 1 is an explanatory diagram of the configuration of the present invention, FIG. 2 is a block diagram showing an example of the hardware configuration of an embodiment of the present invention, and FIG. 3 is a flowchart showing an example of the contents of a test program. In the figure, 1...Bus, 2...Microprocessor (MPU), 3...ROM, 4...RAM, 5...RAM for memory mapped I/O, 6...Input interface, 7...Output interface, 8...Auxiliary memory Control circuit, 9... Input device, 10... Output device, 11... Auxiliary storage device, 20... Storage means for the program to be debugged, 21... Memory for memory mapping I/O,
22... Test program storage means, 23... Output means, 24... Execution means, DP... Program to be debugged, TP... Test program.
Claims (1)
グラムの格納手段と、 前記メモリマツプ化Ｉ／Ｏとして使用するメモ
リと、 該メモリに対し所定の書込み動作と読出し動作
を行なうテストプログラムの格納手段と、 出力手段と、 前記両格納手段に格納された被デバツグプログ
ラムとテストプログラムとを時分割により並行し
て実行し、前記テストプログラムの実行結果を前
記出力手段に出力する実行手段とを具備したこと
を特徴とするプログラムデバツグ装置。[Claims for Utility Model Registration] Storage means for a debugged program having memory mapped I/O, a memory used as the memory mapped I/O, and a test for performing predetermined write and read operations on the memory. A program storage means, an output means, and a program to be debugged and a test program stored in both the storage means are executed in parallel in a time-sharing manner, and an execution result of the test program is outputted to the output means. A program debugging device characterized by comprising means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6200887U JPS63168545U (en) | 1987-04-23 | 1987-04-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6200887U JPS63168545U (en) | 1987-04-23 | 1987-04-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63168545U true JPS63168545U (en) | 1988-11-02 |
Family
ID=30895869
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6200887U Pending JPS63168545U (en) | 1987-04-23 | 1987-04-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63168545U (en) |
-
1987
- 1987-04-23 JP JP6200887U patent/JPS63168545U/ja active Pending