JPH0164745U - - Google Patents
Info
- Publication number
- JPH0164745U JPH0164745U JP1987158306U JP15830687U JPH0164745U JP H0164745 U JPH0164745 U JP H0164745U JP 1987158306 U JP1987158306 U JP 1987158306U JP 15830687 U JP15830687 U JP 15830687U JP H0164745 U JPH0164745 U JP H0164745U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- control unit
- central control
- instruction address
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Debugging And Monitoring (AREA)
Description
第１図はこの考案の一実施例を示す図、第２図
はこの考案の入力設定例を示す図、第３図はこの
考案による表示例を示す図である。
図において、１は中央制候装置、２は主記憶装
置、３は入力機器、４は入力回路、５は制御回路
、６はＣＰＵインターフエイス回路、７ａ，７ｂ
，…７ｎは変換回路、８は出力回路、９は表示機
器、１０，１１，１２，１３，１４，１５，１６
，１７，１８はデータバス、１９，２０，２１，
２２，２３は制御信号である。
FIG. 1 is a diagram showing an embodiment of this invention, FIG. 2 is a diagram showing an example of input settings of this invention, and FIG. 3 is a diagram showing an example of display according to this invention. In the figure, 1 is a central controller, 2 is a main memory, 3 is an input device, 4 is an input circuit, 5 is a control circuit, 6 is a CPU interface circuit, 7a, 7b
,...7n is a conversion circuit, 8 is an output circuit, 9 is a display device, 10, 11, 12, 13, 14, 15, 16
, 17, 18 are data buses, 19, 20, 21,
22 and 23 are control signals.
Claims (1)
囲とを設定する入力機器と、この入力機器の設定
データを処理のため入力する入力回路と、中央制
御装置の実行状況を常に監視するＣＰＵインター
フエイス回路と、上記中央制御装置の実行した命
令アドレスが前記入力されたトレース範囲内の命
令アドレスと一致した時に、上記中央制御装置の
実行を中断させると共に、主記憶装置の命令アド
レスの内容及び上記中央制御装置の各種レジスタ
の内容を読み出して、表示出力形式に変換するた
めの変換回路を起動する制御回路と、上記変換回
路の変換結果を出力する出力回路と、上記出力回
路の出力を表示する表示機器とを有することを特
徴とするプログラムモニタ装置。 An input device that sets the type and scope of tracing of a program in the main memory, an input circuit that inputs setting data of this input device for processing, and a CPU interface circuit that constantly monitors the execution status of the central control unit. , when the instruction address executed by the central control unit matches the instruction address within the input trace range, the execution of the central control unit is interrupted, and the content of the instruction address in the main memory and the central control unit are a control circuit that starts a conversion circuit for reading the contents of various registers and converting them into a display output format; an output circuit that outputs the conversion results of the conversion circuit; and a display device that displays the output of the output circuit. A program monitor device comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987158306U JPH0164745U (en) | 1987-10-16 | 1987-10-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987158306U JPH0164745U (en) | 1987-10-16 | 1987-10-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0164745U true JPH0164745U (en) | 1989-04-25 |
Family
ID=31438511
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987158306U Pending JPH0164745U (en) | 1987-10-16 | 1987-10-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0164745U (en) |
-
1987
- 1987-10-16 JP JP1987158306U patent/JPH0164745U/ja active Pending
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