JPS63143947U - - Google Patents
Info
- Publication number
- JPS63143947U JPS63143947U JP3423887U JP3423887U JPS63143947U JP S63143947 U JPS63143947 U JP S63143947U JP 3423887 U JP3423887 U JP 3423887U JP 3423887 U JP3423887 U JP 3423887U JP S63143947 U JPS63143947 U JP S63143947U
- Authority
- JP
- Japan
- Prior art keywords
- register
- internal
- target cpu
- accessed
- cpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002457 bidirectional effect Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Description
第１図は本考案に係る機能ブロツク図、第２図
はＩ／Ｏレジスタのデータを書き替える場合の動
作フロー、第３図は内部Ｉ／Ｏレジスタのデータ
を読み出して表示させる場合の動作フロー、第４
図は本考案に係るインサーキツト・エミユレータ
の一実施例を示す要部構成図である。
Ａ…エミユレータ本体側、Ｂ…ターゲツトシス
テム、２…アクテイブプログラム実行手段、３…
インターフエイス部、１１…システムＣＰＵ、１
２…システムバス、１３…システムメモリ、１４
…バスコントローラ、１５…制御回路、１６…双
方向メモリ、１７…メモリ、１８…バスマルチプ
レクサ、１９，２０…バス、２１…ターゲツトＣ
ＰＵ、２２…ターゲツトメモリ、２３…ターゲツ
トＩ／Ｏ。
Fig. 1 is a functional block diagram according to the present invention, Fig. 2 is an operational flow when rewriting data in an I/O register, and Fig. 3 is an operational flow when reading and displaying data in an internal I/O register. , 4th
The figure is a diagram showing the configuration of essential parts of an embodiment of the in-circuit emulator according to the present invention. A...Emulator main body side, B...Target system, 2...Active program execution means, 3...
Interface section, 11... System CPU, 1
2...System bus, 13...System memory, 14
...Bus controller, 15...Control circuit, 16...Bidirectional memory, 17...Memory, 18...Bus multiplexer, 19, 20...Bus, 21...Target C
PU, 22...Target memory, 23...Target I/O.
Claims (1)
対象とするインサーキツト・エミユレータにおい
て、 システムＣＰＵとターゲツトＣＰＵがアクセス
可能な双方向メモリと、 前記内部Ｉ／Ｏレジスタ名指定から、その内部
Ｉ／Ｏレジスタのアドレスおよびデータサイズへ
の変換またはその逆の変換が可能なインターフエ
イス部を具備し、 ターゲツトＣＰＵの内部Ｉ／Ｏレジスタに対し
てデータの書き替えあるいはデータの読み出しの
際に、レジスタ名で指定することにより前記内部
Ｉ／Ｏレジスタをアクセスすることができるよう
にしたことを特徴とするインサーキツト・エミユ
レータ。[Claims for Utility Model Registration] In an in-circuit emulator for a target CPU having an internal I/O register, there is a bidirectional memory that can be accessed by the system CPU and the target CPU, and from the specification of the internal I/O register name, It is equipped with an interface unit that can convert the address and data size of the internal I/O register and vice versa, and is used when rewriting data or reading data from the internal I/O register of the target CPU. An in-circuit emulator characterized in that the internal I/O register can be accessed by specifying it by a register name.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3423887U JPS63143947U (en) | 1987-03-09 | 1987-03-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3423887U JPS63143947U (en) | 1987-03-09 | 1987-03-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63143947U true JPS63143947U (en) | 1988-09-21 |
Family
ID=30842598
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3423887U Pending JPS63143947U (en) | 1987-03-09 | 1987-03-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63143947U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02207340A (en) * | 1989-02-08 | 1990-08-17 | Hitachi Micro Comput Eng Ltd | Emulation system and emulator |
-
1987
- 1987-03-09 JP JP3423887U patent/JPS63143947U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02207340A (en) * | 1989-02-08 | 1990-08-17 | Hitachi Micro Comput Eng Ltd | Emulation system and emulator |
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