JPS58109908A - Monitor for sequence controller - Google Patents

Abstract

PURPOSE:To monitor the content of a data memory in a program address selected arbitrarily, by inputting address information of a program to be monitored in a register in advance. CONSTITUTION:In monitoring the content of the data memory 5,100 at the program address 3-street number, address information is inputted to a register R6. When the program executed and a program counter reaches the address 4-street number, a comparison means 7 detects this state and outputs an interruption instruction IR to a CPU1. The CPU1 receiving the IR jumps to a monitor routine and opens a data bus 9 and an address bus 10. In this state, a monitor input/output device 8 accesses a data memory 4 via the address bus 10 and reads and monitors the objective data via the data bus 9.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of a monitor device for a sequence controller. In a monitor device that can be installed or connected to a conventional sequence controller, a sequence controller usually executes program calculations. However, since the configuration is such that the monitoring operation is performed after the transfer with the device, it is not possible to monitor the contents of the data memory during programming, calculations, etc. - The operation of the conventional sequence controller is
As shown in the figure, in step 2, the instruction stored in the program memory is retrieved, a fetch operation is executed to send it to the control unit, and in the next step 2, the instruction is executed [, the next step In step (2), it is determined whether the program has ended or not. If the program has not ended, the process returns to step (1) above. Repeat the same operation, and proceed to the next step ■ when it is determined that 7 is completed τ
The system is configured to perform a % transfer and then perform a Mo=J operation in step (3).

Therefore, for example, a ladder diagram as shown in FIG.
and when contact 001 is on, data memory address 5011
Performs subtraction between the contents of and 5100, and the result is 5
It shows command ports that are classified into 100. . ) is stored in the user memory in the command language shown in Figure 3, the sequence controller executes the program operation according to the flow shown in Figure 1, transfers the % device and ゛, and then executes the monitor operation. do. Therefore, when the Add instruction is executed at the program address 3, the result is stored in the data memory address 5100, but when the 5tJ4 instruction is executed at the program address information location, the result is also stored in the same data memory address.
It was not possible to monitor the stored data that was executed previously.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a sequence controller monitor device that can monitor the contents of a data memory at an arbitrarily selected program address. To achieve this purpose, a monitor device for a sequence controller according to the present invention includes a user memory for storing fljH1''-f programs, a program counter for specifying the address of the program stored in this user memory, and data for storing data. a memory, an address register for specifying the address of this data memory, an input means for inputting program address information to be monitored, a storage means for storing address information input from the input means, Comparing means for comparing the contents of the data memory with the contents of the storage means and issuing an interrupt instruction according to the comparison result, and control means for outputting the stored contents of the data memory according to the interrupt instruction. The system is configured so that an interrupt can be applied to any address during program execution to monitor the stored contents of the internal data ν at the time of the program address.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 4 is a block diagram showing the configuration of an apparatus according to an embodiment of the present invention.

In FIG. 4, l is a central processing unit (CPU) that executes various calculation controls, 2 is a user memory that stores user programs, 3 is a program counter that specifies the program address of the user memory 2, and 4 is a data 5 is an address register for specifying the address of the data memory 4; 6 is a register R (storage means) for inputting and storing program address information to be monitored; and 7 is a register R for storing the contents of the program counter 3 and the register R. (Storage means) Comparison means 8 compares the contents of 6 and derives an interrupt instruction IR to the CPU 1 based on the comparison result. The above register R (
The CPU 2, user memory 2, data memory 4, and monitor input/output device 8 are connected to each other by a data bus 9, and the user memory 2, program color/ ri3,
Data memory 4, address register 5, and monitor input/output device 8 are interconnected by address bus 10.

Next, the operation of the above-mentioned apparatus will be explained in accordance with the operation flowchart shown in FIG. 5, taking as an example the case where the program shown in FIG. 3 is executed.

If it is desired to monitor the contents of the data memory 5100 at program address 3, the input means of the monitor input/output device 80 is operated to input and store address information (3+1) into the register R (storage means) 6. In this state, the sequence controller executes the program stored in the user memory 2 according to the operation flow shown in FIG.
, and the result of the calculation is stored again at address 5100 (execution of step (2)). After execution of this operation, the program counter is increased by 1 and becomes address 4, and the sequence controller operation returns to step ① again. After fetching the STR instruction at address 4, it moves to step 0 and an interrupt instruction is issued. On the other hand, at this stage, the contents of the program counter 3 and the register R (storage means) 6 are both at address 4 and match, so the comparison means 7 detects this state and sends a message to the CPU. and outputs an interrupt instruction IR. Upon receiving this interrupt instruction IR, the CPU jumps to the stage [phase] monitor routine and releases the address bus 9 and data bus IO. In this state, the monitor input/output device 8 accesses the data memory 4 via the address bus 10t, reads the target data via the data bus 9, and monitors it.

When this monitor operation is completed, the CPUI returns from the monitor routine to the main program routine of phase [phase] to continue commanding.

As described above, it is possible to interrupt an arbitrary address during program execution and monitor the state of the internal data memory at the time of the program address.

As described above, according to the present invention, the address information of the program to be monitored by the monitor device is inputted in advance to the register R (storage means), and the address information of the program to be monitored by the monitor device is input in advance to the register R
By comparing the contents of the (storage means) and the counter, it interrupts the CPU and monitors the contents of the data memory, so the data at any program address, the memory You can monitor the contents of

Furthermore, since the contents of the data memory at any program address can be monitored in this way, the data memory area can be used twice, which has the advantage that the data memory capacity of the sequence controller can be reduced.

[Brief explanation of the drawing]

Figure 1 is an operation flow diagram of the conventional device, Figure 2 is a ladder diagram,
FIG. 3 is a diagram showing the program storage state, FIG. 4 is a block diagram showing the configuration of an embodiment of the apparatus of the present invention, and FIG. 5 is an operation flow diagram for explaining the operation. 1... Central processing unit, 2... User memory,
8...Program counter, 4...Data memory,
5...Address register, 6...Register R (note (
i [means), 7... Comparison means, 8... Monitor input/output device, IR... Interrupt instruction. Agent Patent Attorney Aihiko Fuku 35

Claims (1)

[Claims] 1. In a stored program type sequence controller, a user memory λ that stores a user program, a program counter that specifies the address of the program stored in the first memory, a data memory that stores data, and the address of the data memory. an address register for specifying the program address information to be monitored, an input means for inputting program address information to be monitored, a storage means for storing the thick address information input from the input means, and a storage means for storing the contents of the program counter. a comparison means for comparing the contents of the information and displaying an interrupt instruction according to the comparison result;
A monitor device for a sequence controller, comprising control means for outputting the stored contents of the data memory in response to the interrupt command.