JPS6015970B2 - Interrupt processing device in microprocessor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interrupt processing device that interrupts a microprocessor in response to an external interrupt request. The object of the present invention is to increase response time and shorten the time from when an interrupt request is received until the corresponding processing is started, thereby improving responsiveness.

In recent years, microprocessors have come to be used in many fields, and a large number of microprocessors with different functions are being sold by domestic and foreign semiconductor manufacturers. However, in these microprocessors, there are only a few types of interrupts, and the maximum number of interrupts is about 8 to 1, so when performing different types of arithmetic processing using external interrupts, it is necessary to The types were limited by the type of interrupt, and a single microprocessor could not perform arithmetic processing of more types than the types of interrupts. On the other hand, the number of flags that store external interrupt requests is set according to the type of interrupt, and by testing which flag is set in a program, the type of interrupt can be identified, and calculations can be performed according to the type of interrupt. There is also a method of processing, and using this method, it is possible to perform many types of arithmetic processing with one type of microprocessor interrupt, but in this method, the interrupt flag is tested by software every time an interrupt is processed. Therefore, it takes time from when an interrupt request is given until the arithmetic processing starts, and the arithmetic processing cannot be performed in a short time.

The present invention has been made in view of this point, and when an interrupt request is received from an external source, an interrupt signal is supplied to the microprocessor in response to the interrupt request, and the process in progress is interrupted. , in response to this interrupt, outputs a branch instruction on the data bus that directs a branch to a specific address, changing the humble address of the microprocessor to a specific address; The memory address includes an instruction generation circuit that stores in memory a program that jumps to a specific address that is not in the memory, and outputs a simulated subroutine call instruction or unconditional jump instruction to the specific address; An address register is provided to temporarily store the memory address of the jump destination of this subroutine instruction or unconditional jump instruction, and the contents of this address register are rewritten by an interrupt request given from the outside or memory address data of the jump destination given from the outside. This feature is characterized in that the jump destination address can be changed arbitrarily. Embodiments of the present invention will be described below based on the drawings. In FIG. 1, reference numeral 1 denotes a computer mainly configured with a microprocessor 10, a memory 11, and an input/output board 12.
a to 12n, and an input/output boat selection circuit 13. As the microprocessor 10, a microprocessor equivalent to Innel 808 is used in this embodiment.
This 808 rare microprocessor 10 has a memory 11
The input/output ports 12a to 12n are specified using 16 bits, and arithmetic processing is performed using 8 bits.
16-bit memory address terminals MAO to MA15 and 8
It has bit data terminals DO to D7. This 16
The memory address terminals MAO to MA15 of the bits are connected to the memory 11 and the input/output boat selection circuit 13 via the address bus AB, and the address data output from the microprocessor 10 is connected to the memory 11 and the input/output boat selection circuit 13 via the address bus AB. 13 and given.

Thereby, selection of a memory address or selection of input/output ports 12a to 12n is performed. Also, data terminal D
O to D7 are connected to the memory 11 and the input/output boats 12a to 12n via the data bus DB, and data can be exchanged between the microprocessor 10 and the memory 11 and the microprocessor 10 and the input/output boats T2a to 12n. It will be done. The memory 11 is composed of a core memory or a semiconductor memory, and stores programs for arithmetic processing performed by the microprocessor 10.

As shown in FIG. 2, this memory 11 stores, in addition to the main program, a large number of subroutine programs for performing various arithmetic operations in response to interrupt requests from the outside. A stack area is also provided for executing branch instructions. Input/output boats 12a-12
n is for exchanging data between the external devices 2a to 2n and the computer, and these input/output ports 1
2a to 12M are enabled when a signal is applied from the input/output boat selection circuit 13. On the other hand, an interrupt request signal IRQ is output from the external devices 2a to 2n, and an interrupt request is made to the computer 1.
The computer is also connected to an external computer 3 via an input/output port 12s. The external computer 3 is, for example, a high-speed arithmetic processing device dedicated to condition determination, which is composed of an Intel microprogram controller 3001 and a microprogram memory. It is designed to perform sequence control of machine tools, etc. (not shown).

Since this external computer 3 is only for condition judgment and does not have an arithmetic processing function, it cannot execute arithmetic instructions such as timer instructions and counter instructions in the sequence program. These arithmetic instructions are executed on behalf of the computer by interrupting them. Also, when outputting the contents of the main memory 4 to the external devices 2a to 2n in response to a command from the external devices 2a to 2n, an interrupt is applied to the computer 1 to mediate data transfer and perform data conversion. let Therefore, an interrupt request signal IRQ is given from the external computer 3 to the computer 1, and this interrupt request signal IRQ is
In parallel with the sending of Q, data at the starting memory address of the arithmetic processing program to be executed is sent to the computer 1. Therefore, when the computer 1 receives the interrupt request signal mQ from the external computer 3, it can jump to the memory address sent from the external computer 3 and perform arithmetic processing. In order to receive such an interrupt request and cause the microprocessor 10 to perform an interrupt operation, the computer 1 includes an OR gate, a delay circuit 14, a status latch 15, an RST instruction generation circuit 16, a CALL instruction generation circuit 17, and an address register 8. , RET instruction generation circuit 19, address selector 21, read-only memory 22, and gates GI to G6.

The interrupt request signal IRQ sent from the external devices 2a to 2n and the external computer 3 is given to the input terminal of the OR gate OR, and the interrupt request signal IRQ is sent from either the external devices 2a to 2n or the external computer 3. I
When RQ is sent out, a signal is output from the OR gate OR.

The signal output from this OR gate is the delay circuit 14.
The signal is delayed by a time corresponding to the data read time of the address register 18, which will be described later, and is applied to the interrupt terminal INT of the microprocessor 10. When a signal is applied to this interrupt terminal T, the microprocessor 10 recognizes that an interrupt request has been made from the outside.

Then, after the microprocessor 10 completes the instruction currently being executed, the synchronization signal SYNC is activated in the next machine cycle.
In synchronization with this, data representing recognition of the interrupt request is sent to the data bus DB. Data representing recognition of this interrupt request is read by the status latch 15 which latches information on the data bus DB in response to the synchronization signal SYNC, and the status latch 15 outputs an interrupt recognition signal TA. The interrupt recognition signal INTA output from the status latch 15 is given to the RST command generation circuit 16, and when the interrupt recognition signal NTA is sent from the status latch 15, the RST
An RST instruction for branching from the main routine to a subroutine is output from the instruction generation circuit 16 to the data bus DB. When this RST instruction is output to the data bus DB, the microprocessor 10 reads the RST instruction and
Execute the RST command.

This RST instruction is a 1-word branch instruction with an instruction code of 1.
By setting the AAA part of 1AAAIII in advance, it is possible to arbitrarily jump to every eighth memory address from address 0 to address 5. Further, the start memory address of the program to be executed next to the main routine whose execution has been interrupted is stored in a pushdown stack provided in the memory 11. In this embodiment, the code 11111111 is generated as the RST command, and when an interrupt request is given, the main routine jumps to the 5th line.
As shown in Figure 2, an unconditional jump command JMP is programmed in memory 1 1, 5 Mochi Flea, and when the program for 5 Mochi Flea is read out, the jump destination programmed in 57, 5 Charged Flea is programmed. Jump to Doji at address 2000.

This address of 2000 is not in the memory 11, and the CALL command generation circuit 17 serves as a data area corresponding to address 20000.

This CALL instruction generation circuit 17 outputs a subroutine call instruction code 11001101 in a simulated manner, and the data output from this CALL instruction generation circuit 17 is output to the data bus DB via the gate GI. There is. The address register 18 is a 16-bit register that temporarily stores the start memory address of the subroutine to jump, and the upper 8 bits are 20001.
It corresponds to the data area of the address and corresponds to the data area of the lower 8 bits 20002 crabs. Then, the upper 8 bits of the address data stored in this address register 18 are outputted to the data bus DB via the gate G2.
The lower bits are output to data bus DB via gate G3. Furthermore, a RET command generation circuit 19 is provided corresponding to the data area at address 20003. This RET instruction generation circuit 19 outputs a return instruction code 11001001 in a simulated manner, and the data output from this RET instruction generation circuit 19 is output to the data bus DB via the gate G4. There is. Note that the subroutine call instruction CALL output from the CALL instruction generation circuit 17 stores the start address of the next instruction stored outside the program counter in the microprocessor 10 in the pushdown stack, and then stores the start address of the next instruction stored outside the program counter in the microprocessor 10. This is an instruction that sets two words of address data following the CALL instruction and jumps to the memory address specified by this address data.The return instruction RET, which is generated from the RET instruction generation circuit 19, is sent to the pushdown stack. This command reads the stored data, sets it in the program counter, and returns to the original routine.

The address decoder 20 opens and closes the gates GI to G4, and inputs memory address data output from the microprocessor 10.
The memory address output from 2000~2
When the power is in the 000 group, gates GI to G4 are opened.

Therefore, by executing the unconditional jump command JMP stored in the memory 11, the program 2
When you jump to address 0000, Gate GI will open,
A CALL command is given to microprocessor 10 via data bus DB. As a result, the microprocessor 10 processes the CALL instruction. First, the start address of the next instruction stored in the program counter, that is, the address 20003 of the RET instruction, is stored in the bushdown stack in the memory 11.
The address data stored at address 1 and 20002, that is, the address data stored in the address register 18, is read and set in the program counter. This causes the program to write address register 1
The subroutine program jumps to the start address of the subroutine stored in 8, and the subroutine program is executed. In addition, a RET command is programmed after the subroutine program, and when this RET command is executed after the subroutine program is executed, the data stored in the pushdown stack at memory address 20003 is transferred to the microprocessor. A processor within processor 10.

RET of 2000 points set in gram counter
The command is executed. As a result, the address data stored in the pushdown stack one time before the 2000-line data, that is, the memory address of the main routine stored by executing the RST instruction, is pushed out.
The gram counter is set and the program returns to the main routine. The circuit formed by the address selector 21, read-only memory 22, gates G5, G6, and inverter W is stored in the address register 18 depending on the type of interrupt generated from the external devices 2a to 2n or the external computer 3. This is a circuit that rewrites the jump destination memory address in the read-only memory 22.
Data at the start memory address of a subroutine program corresponding to the type of interrupt request sent from the external devices 2a to 2n is stored in advance in each memory area.

For example, a subroutine program corresponding to an interrupt request from the external device 2a is stored at addresses 5000 to 500 of the memory 11, and a subroutine program corresponding to an interrupt request from the external device 2b is stored at addresses 5010 to 5022. If there are subroutine programs, the start addresses 5000 and 5010 of these subroutine programs are stored in the read-only memory 22. The address input terminal ADD of the read-only memory 22 is connected to the output terminal of an address selector 21 that outputs address data according to the type of interrupt request signal IRQ generated from the external devices 2a to 2n. Interrupt request signal I from devices 2a to 2n
When RQ is applied, data at the start memory address of the subroutine program corresponding to the type of this interrupt request signal is output from the read-only memory 22. Then, the memory address data output from the read-only memory 22 is passed through the gate G5 to the address register 18.
It is beginning to be given to On the other hand, the data at the start address of the subroutine program output from the external computer 3 is given to the address register 18 via the gate G6, and the gate G6 is connected to the interrupt request signal IRQ output from the external computer 3. The gate G5 is opened by a signal obtained by inverting this interrupt request signal IRQ by an inverter IV.

Therefore, when there is an interrupt request from the external computer 3, the gate G6 is opened and the external computer 3
Gate G5 is opened if no interrupt request is given from. Also, the load terminal LOA of the address register 18
A signal output from the OR gate OR is given to D, and when an interrupt request signal IRQ is given from the external devices 2a to 2n or the external computer 3, the signal is output from the external computer 3 or the read-only memory 22. The data at the memory address is stored in address register 1.
The jump destination subroutine is changed depending on the type of interrupt. Next, the operation of the interrupt processing device having the above configuration will be explained.

Now, suppose that an interrupt request is received from the external device 2b during the execution of the May program, and an interrupt request signal mQ is given to the computer 1.This interrupt request signal IRQ is given to the OR gate OR and the address selector 21. . When the address selector 21 is given the interrupt request signal IRQ from the external device 2b, the address selector 21 specifies the address of the read-only memory 22, and the read-on IJ memory 22 responds to the interrupt request from the external device 2b. Data 5010 at the start memory address of the subroutine program is output. At this time, the interrupt request signal IRQ is not output from the external computer 3 and the output of the inverter IV is "H'', so the gate G5 is open and the read-only memory 22 outputs the Data 5010 of the memory address
is given to address register 18. On the other hand, since the interrupt request signal IRQ is also applied to the input terminal of the OR gate OR, a signal is output from the OR gate OR, and this signal is applied to the load terminal LOAD of the address register 18. As a result, the memory address data 5010 output from the read-only memory 22 is read into the address register 18. In this way, the external device 2b
When the reading of data 5010 at the start memory address of the subroutine program in response to an interrupt request from the microprocessor 10 is completed, a signal is output from the delay circuit 14, and the signal is applied to the interrupt terminal mT of the microprocessor 10.

Then, the microprocessor 10 recognizes that there is an interrupt request from the outside, and executes the program ADD at address 384 in the next machine cycle where the interrupt occurred.
If an interrupt occurs during execution of program M, a status signal indicating recognition of the interrupt is output to data bus DB in the next machine cycle after executing program ADDM. When a status signal representing recognition of an interrupt is output on the data bus DB, this signal is read by the status latch 15, and the interrupt recognition signal INTA is sent from the status latch 15 to the RST command generation circuit 16. As a result, the RST command generation circuit 16 outputs memory address 5.
Code 111111 of RST command to jump to dead area
11 is output, and this code is given to the microprocessor via the data bus DB.

Then, the microprocessor 10 stores the data 385 at the start memo IJ address of the next program that was interrupted in the pushdown stack in the memory 11, and then
Jump to memory address 5-phrase electric field. Since the unconditional jump command JMP is programmed in this memory address 5, the program unconditionally jumps to the jump destination address 2000 programmed in the 5-way address $.

This jump destination address 2000 is memory 1
The address decoder 20 decodes that the address output from the microprocessor 10 is not in the area 1 and is in the area 2000. As a result, the gate GI is opened, and the instruction code 11001 of the subroutine call instruction generated by the CALL instruction generation circuit 17
101 is connected to the microprocessor 1 via the data bus DB.
given to 0. When the instruction code for a subroutine call is given to microprocessor 10', microprocessor 10 sets the program counter to
Data 20003 at the start address of the program following the CALL instruction is stored in the pushdown stack, and then data at addresses 20001 and 20002, that is, data 501 stored in the address register 18, is stored in the pushdown stack.
Set 0 to the program counter.

This causes the program to jump to the 501 location,
The subroutine program corresponding to the interrupt request from the external device 2b stored from 501 to 5022 is executed. When the arithmetic processing and data exchange in response to the interrupt request from the external device 2b are completed by executing the subroutine program, a return instruction RET is executed at the end of the subroutine program.

When this return instruction RET is executed, the memory address data 20003 that was last stored in the pushdown stack is read out and set in the program counter. This will jump to address 20003 and 20
002 Oath turn command RET is executed. As a result, the memory address 3 of the next main program with the interrupt that was first stored in the pushdown stack is
85 is pu. The gram counter is set and the program jumps to 385 Flea and returns to the main program. In this manner, when the subroutine program is completed, the main program is repeatedly executed until the next interrupt request is given.

Subsequently, when an interrupt occurs from the external device 2a, the read-only memory 22 outputs the start memory address 5000 of the subroutine program corresponding to the interrupt request from the external device 2a, and stores it in the address register 18. The jump destination address stored in the memory is rewritten, and after this, the microphone.

An interrupt is placed on processor 10. As a result, the microprocessor 10 interrupts the execution of the main program and performs a jump operation in the same manner as in the previous case.
Execute subroutine programs from 0 to 500. When the execution of this subroutine program is completed, the main program will be executed again. On the other hand, when there is an interrupt request from the external computer 3, the gate G5 is closed and the gate G6 is opened, so that the data at the memory address representing the start address of the subroutine program output from the external computer 3 is stored in the address register. 8 will be given.

As a result, the microprocessor 10 jumps to the memory address output from the external computer 3, executes a predetermined subroutine program, and executes the main program again. Therefore, by changing the memory address output from the external computer 3,
A number of different subroutine programs are executed, and various data representing the execution results of the subroutine programs are transferred to the external computer viewer 3. in this way,
By having the computer 1 perform various arithmetic processes, it is possible to perform sequence control including timer and counter operations even when using an external computer that can only perform condition determination, as well as correcting and monitoring sequence programs. etc. can be done easily.
In the above embodiment, the external computer 3 directly outputs the memory address of the jump destination, but the external computer 3 outputs data indicating the type of interrupt, and this data is stored in the read-only memory. The address may be converted into a jump destination address and provided to the address register 18.

Furthermore, in the above embodiment, the subroutine jump instruction CALL is used as the instruction to jump to the subroutine, but if it is not necessary to always search the main program, the subroutine call instruction CALL may be used as the unconditional jump instruction JMP. .

In this case, it is necessary to provide a flag for storing the completion of the subroutine and to set or reset this flag at the end of the subroutine program to control acceptance of interrupts from the outside. Furthermore, in the above embodiment, the circuit that determines the priority of interrupts and the circuit that stores interrupt request signals are omitted to simplify the explanation, but these circuits are necessary in an actual device. becomes.

As described above, in the interrupt processing device of the present invention, the memory stores a program that jumps to a specific address not in the memory in response to an interrupt request given to the microprocessor. The system is equipped with an instruction generation circuit that outputs a subroutine call instruction or an unconditional jump instruction, and an address register that temporarily stores the memory address to which the subroutine instruction or unconditional jump instruction jumps. Since the data is rewritten according to the interrupt request received or the memory address data of the jump destination, it is possible to jump to any subroutine by rewriting the address register, and interrupts can be processed without being limited by the type of interrupt of the microprocessor itself. It has the advantage of being able to perform many types of arithmetic processing.

Furthermore, in the present invention, when an interrupt request is received from the outside, an interrupt signal is sent to the microprocessor in response to the interrupt request, interrupting the process in progress, and responding to the interrupt. Then, a branch instruction to branch to a specific address is output on the data bus, and the read address of the microprocessor is changed to a specific address, so when an interrupt request is received from the outside, It is possible to immediately branch to a jump destination address in response to an interrupt, which has the advantage of good responsiveness.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a computer equipped with an interrupt processing device according to the present invention, and FIG. 2 is a memory map showing the storage state of the memory in FIG. 10...Microprocessor, 11...Memory, 15.
...Status latch, 16...RST command generation circuit, 17...CALL command generation circuit,
18...Address register, 19...RE
T instruction generation circuit, 20...address decoder, 21
...Address selector, 22...Read only memory, GI to G6...Gate, mQ...Interrupt request signal. moth, spear and figure

Claims (1)

[Claims] 1 An interrupt processing device that increases the types of microprocessor interrupts that jump to a predetermined memory address in response to an external interrupt request and execute a program from the jumped memory address, and that responds to an external interrupt request. an interrupt signal supply circuit that interrupts execution of processing by supplying an interrupt request signal to the microprocessor; and a branch to a specific memory address in response to interrupt recognition data output from the microprocessor. a first instruction generation circuit that outputs a branch instruction to the data bus, and a jump instruction that sets a specific address not in the memory as a jump destination address is programmed in the specific memory address; , a second instruction generation circuit that is provided corresponding to this specific address and outputs a simulated subroutine call instruction or an unconditional jump instruction, and a memory address to which the jump is to be temporarily stored prior to acceptance of the interrupt request. an address register that inputs memory address data output from the microprocessor and detects that data at the specific address has been output; a gate circuit that outputs a subroutine call instruction or an unconditional jump instruction outputted from an instruction generation circuit and a memory address stored in the address register to a data bus connected to the microprocessor; and a jump destination given from the outside. 1. An interrupt processing device for a microprocessor, comprising: address changing means for rewriting the contents of the address register in accordance with memory address data of the processor to change a jump destination memory address.