JPS5987555A - Hash total checking system of microprogram rom - Google Patents

Abstract

PURPOSE:To execute by a program which is simple and has a small number of steps by switching to a program and a data for deriving a hash total value, when a microcomputer reads the contents of a microprogram ROM. CONSTITUTION:A read flag showing that an ROM3 is reading out a data, and an upper address are set into a register 8 of a register 1. Subsequently, the read flag and the upper address of the ROM3 are set to a B port. Next, the data of the ROM3 is set to an accumulator 10 by using the contents of a register 0 as a lower address, and the contents of a register 2 are added and stored in the register 2. The contents of the register 0 are added by ''1'', whether a hash total check of one page portion is ended or not is checked, and when it is ended, the upper address of the ROM3 is added by ''1''. Whether a hash total value of all data is derived or not is decided, and when it is a prescrived value, it is normal, and if it does not become said value, it is decided that said check is ended abnormally.

Description

[Detailed Description of the Invention] The present invention is a system for performing a so-called no-sh total check in which data stored in an external microprogram ROM of a microcombinator is sequentially added and the total value is checked. It is related to the method.

Conventionally, in microcomputers that do not have such a built-in microprogram ROM, the contents stored in the external microprogram ROM can only be referred to within the host where the program is stored and from the stored wave. - There is a limit of 3 pages from the page, and there is a limit to the badge of the micro program ROM. was not carried out.

The present invention has been made in view of this point, and includes a signal indicating that data stored in a microprogram ROM that can be set and reset by a microcomputer is being read, and a signal that indicates that data stored in a microprogram ROM is being read. A circuit is constructed in which a readout signal is combined with a signal for the microcomputer to read data on the data bus, and the combined signal is connected to the chip enable terminal of the microzologram ROM, and the data is stored in the microprogram ROM. When reading the contents simply as data for calculating the hash total value, treat the microprogram ROM not as program memory but as a normal external storage device, and use the external storage device read command to store it in the microprogram ROM. This provides a method necessary for a complete hash check of a microprogram ROM that can be implemented with a simple program with a small number of steps.

A detailed explanation will be given below according to examples.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention,
FIGS. 2 and 3 are a time chart and a flow chart, respectively, for explaining the operation.

In FIG. 1, 1 is a microcomputer.

2 is an address/latch circuit, 3 is a microprogram/
ROM, 4 is AND gate, 5 is inverter circuit, 6
is the or gate.

Preferably, the microcomputer 1 is an Intel 80
The address latch circuit 2 is a 5N74L8373, and the microprogram ROM 3 is a 2732 EB ROM (rewritable read-only memory) manufactured by Intel Corporation.

As is well known, the microcomputer 1 includes an arithmetic unit 7, a register 8. Data storage section 9. Accumulator 10, ■ angle (
In/output) port 11° control section 12
．． It consists of an internal path 13 and an instruction analysis section 27.

The A port of I10 port 11 connected to line 14 and the B port of I10 port 11 connected to line 15 have latch circuits in their output parts, but the C port of I10 port 11 connected to line 16 has There is no latch circuit in the output section, and an address latch circuit 2 for the microprogram ROM is provided externally.

The timing signal for latching the address of the address latch circuit 2 is transmitted to the microcomputer 1 as shown in FIG. 2(a).
from the control mill section 12 via line 21.

Lines 17 and 2-in-18 are the address signal lines of microprogram ROM 3, and line 19 is the data signal line of microprogram ROM 3 addressed by lines 17 and 18, which is valid only through line 24. This is only when the chip enable signal applied to the microprogram ROM 3 is at a low level.

A line 22 connected to the control unit 12 is a signal line for the microcomputer 1 to read the program stored in the microprogram ROM 3.
3 is a signal line through which the microcomputer 1 reads data stored in the microprogram ROM 3 as an external storage device.

Note that the other ends of the lines 14 and 15 are connected to a control device that is not directly related to the present invention.

Next, referring to the time chart of FIG. 2, the external storage device read command, that is, the operation performed in the step ○ in FIG. 3 in which the microcomputer 1 reads data stored in the microprogram ROM 3 will be described.

An instruction to read data stored in such an external storage device is processed in two machine cycles: an instruction fetch cycle and an I10 read cycle (2), as shown in FIG. 2(a).

First, in the instruction fetch cycle (■), the lower part of the contents O of the program color in FIG. The latch circuit 2 is connected to the latch circuit 2 via the line 21 from the control section 12 of the
The address latch circuit 2 is latched by the address latch enable signal shown in FIG. Incidentally, during the instruction fetch, the upper part of the symbol (2) in FIG. 2(d) is stably outputted on the line 17 by the microcomputer 1. The signal latched by the address latch circuit 2 is applied to the microprogram ROM 3 via a line 18, and together with the signal on the line 17 indicates the storage address of the program stored in the microprogram ROM 3. Used as a temporary address signal.

Next, from the storage location of the microprogram ROM 3 specified by the address signal, the data indicated by ◎ in FIG. 22. The microprogram ROM 3 chip enable terminal (CE
) is given the program store enable signal shown in FIG. The instruction fetch cycle is then transferred to and analyzed, and the instruction fetch cycle is completed.

Next, an I10 read cycle (2) begins according to the instruction fetched in the instruction fetch cycle (2).

First, the lower part of [F] in FIG. 2(d), which is specified by the program and indicates the address of the microprogram ROM 3 to be read, is the address in FIG. 2(a).
It is latched into the address latch circuit 2' by the latch enable signal.

Incidentally, at this time, the upper address of the above [F] indicating the address of the microprogram ROM 3 has already formed part of the line 15 with an instruction to set data to the B port of the I10 port 11 connected to the line 15. It is output on line 17. For example, the step θ in FIG.

Also, by the above command, the microprogram ROM 3 is placed on one line 2θ of line 15 excluding line 17.
FIG. 2 (e
) is output.

Next, the address signals of the upper and lower parts of [F] in FIG.
8 to the microprogram ROM 3, and the data shown in FIG.
] is ready to be read.

When the microcomputer 1 outputs the external storage device read command shown in FIG. The signal shown in FIG. 2(c) indicating that data currently being read is being read is logically operated by the inverter gate 5, and is combined with a low level signal output on line 26 and an external storage device read command signal on line 23. are logically ORed by the OR gate 6, and a signal such as the delayed one of FIG. 2(c) is sent to the line 25. Chip enable terminal (CE) of microprogram ROM 3 via AND gate 4 and line 24
The data [F] shown in FIG.
and is applied to the microcomputer 1 via the I10 port 11 and the tr-ports.

Up until now, we have described the circuit and method by which the microcomputer 1 reads the data stored in the microprogram ROM 3 as an external storage device. The check will be explained in detail with reference to FIG. The registers described below are components of the internal register 8 of the microcomputer 1.

First, in step (2), register O, which stores the lower address for reading data stored in the microprogram ROM 3, and register 2, which stores the hash total value, are cleared. Next, in step @, the read flag indicating that data stored in the microprogram ROM 3 is being read and the microprogram O
Data of '0' is set in register 1, which stores the upper address of ROM 3, except for the read flag.

Next, in step O, the upper address of the microprogram ROM 3 is set to the B port connected to the line 15 using the read flag stored in the register 1. At this time, a read flag signal is output on line 20, and an upper address of the microprogram ROM 3 is output on line 17.

Next, in step @, the data stored in register 0 is used as the lower address of microprogram ROM 3 using an external storage device read command, and the address indicated by register 0 and register 1 of microprogram ROM 3 is used in the above circuit. The data stored in microcomputer 1
Accumulator 10 via Ilo, g-to 11
Store in. Next, in step (2), the contents of the aforementioned accumulator and the contents of register 2 storing the hash total value are added and stored in register 2. Next, in step 0 of O, 1 is added to the register O storing the lower address of the microprogram ROM 3, and the lower address of the Nu microprogram ROM 3 is updated by 1. Next, in step ■, it is determined whether or not the total check for 1 to 256 bytes (for example, 256 bytes) has been completed, and if it has not been completed, the process returns to step ○, and when it is completed, ■
Proceeding to step 0, the upper address of the microprogram ROM 3 is memorized, and 1 is added to the soster 1 to update the upper address of the microprogram ROM 3 by 1. Next, in step ①, all data stored in the Micro 70 program ROM 3 is stored.

Determine whether the badge total value has been calculated, and if not all have been completed, return to step θ, and if all have been calculated, proceed to step ■ until the calculated badge total value is a predetermined value. If the hash total value does not reach the predetermined value, it means that the process has ended abnormally.

As described above in detail, according to the present invention, a signal indicating that data stored in a microprogram ROM which can be set and reset by a microcomputer is being read, and a signal indicating that data stored in a microprogram ROM is being read, The microcomputer uses the microprogram ROM as an external storage device to logically calculate the signal for reading the 0 program and the signal for reading the data stored there, and determines whether the output data of the micro program ROM is valid or not. A circuit is provided in which a signal obtained by the logical operation is connected to a chip enable terminal for controlling invalidation, and when the microcomputer reads the contents stored in the microprogram ROM, the contents are read by 7 degrees.
By making it possible to switch between the program and the data used to calculate the total value, the total check of the micro program and the program ROM can be easily performed using a program with a small number of steps.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of a device for reading data stored in a microprogram ROM according to the present invention, FIG. 2 is a time chart for explaining the operation of FIG. 1, and FIG. 1 is a flowchart showing an example of a grogsim for performing a no-shut total check of a microprogram ROM using the circuit shown in FIG. 1. Microcomputer, 2. Address latch circuit, 3. Microprogram ROM. Patent Applicant: Oki Electric Industry Co., Ltd. (Figure 1, Figure 2 (1)) −−−−−−−−−−−−1−−−−−
-te)L

Claims (1)

[Claims] Microcomputer and external microprogram
In a device configured with a ROM (read-only memory), a signal indicating that data stored in the microprogram ROM is being read, which can be set and reset by the microcomputer, and a signal indicating that data stored in the microprogram ROM is being read, The signal for reading the program stored in the ROM and the signal for the microcomputer to read the data on the data bus are logically operated to determine whether the output data of the microprogram ROM is valid or not.
A circuit is provided in which a signal obtained by the logical operation is connected to a chip enable terminal for controlling invalidation, and when the microcomputer reads the contents stored in the microprogram ROM, the contents are exchanged with the program.
17. A microprogram ROM total check method characterized by being switchable between data for determining a total value.