JPS61157944A - Microprocessor with microprogram control part - Google Patents

Abstract

PURPOSE:To inspect efficiently the action of a mapping array by modifying contents of a mapping array control register with the aid of a micro instruction stored in a control memory. CONSTITUTION:The mechanical language of an instruction register 1 is decoded by the mapping array 2, and its address accesses to the control memory 4, whereby the micro instruction is stored in a micro instruction register 5. The micro instruction is decoded by a decoder 7 to execute a transfer instruction, and data is stored in the mapping control register 8 through a control line 200. Simultaneously an address register 3 is updated, and the next micro instruction is accessed from the control memory 4 and stored in the register 5. Its instruction is executed, and control lines 201, 203 and 204 are activated from the decoder 7. Then the state of the mapping array 2 is transferred to a general- purpose register 10 through a logical arithmetic device 11 and a bus 300.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Use The present invention relates to the configuration of a control section of a microprocessor when the control section is implemented using a microprogram control system.

2. Description of the Related Art In the configuration of a control section using a conventional microprogram control method, for example, Nikkei Electronics 1981.4
．． 13P, 122, a method has been proposed in which hardware designed to facilitate testing is added to the basic components of a normal microcontroller.

FIG. 3 shows the configuration of the control unit of this conventional microprocessor, in which 1 is an instruction register for storing machine language instructions, 2 is a mapping array for decoding machine language instructions, and 3 is a mapping array for decoding machine language instructions.
is a control memory address register that holds the output of the mapping array 2, 4 is a control memory that stores a microprogram, 6 is a microinstruction register that holds microinstructions output from the control memory 4, and e is an external device of the microprocessor. and an input/output multiplexer that controls data transfer within the microprocessor.

Further, 100 is a path for transmitting serial data from an external device to the instruction register 1, 101 is an internal serial data meridian, and 10
A signal line 2 serves as a route for sending the contents of the control storage address register to an external device.

In the configuration of the conventional microprocessor control unit configured as described above, when verifying the operation of the mapping array 2, which is a machine language instruction decoding device, the instruction register 1 is specified from the serial data input path 100. Verification is performed by inputting a pattern and outputting the contents of the control storage address register 3, in which the decoded output for that pattern is stored, using the serial data output path 102. The internal serial path 101 is used to check whether the input pattern has been correctly input internally.

Problems to be Solved by the Invention However, in the configuration described above, in the configuration of the instruction register 1 and the control storage address register 3, in addition to the function as registers, it is also possible to receive serial data input/output command control from an external device. , the need to add hardware that functions as a shift register,
In addition, when verifying the mapping array 2, there is a problem that accurate verification cannot be performed because the control timing during the verification process and the control timing during actual operation are significantly different in evaluating the margin of access time, which is its operational characteristic. was.

SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a configuration of a microprocessor control unit that can efficiently verify the operation of a mapping array that is the core of the instruction decoding function in the microprocessor control unit.

Δ Means for Solving the Problem The present invention has an instruction register that stores machine language instructions, a mapping array that takes the output of this instruction register as input and outputs instruction decoding information, and holds the output of this mapping array. A control memory address register, a control memory that stores a microprogram that is accessed by the contents of this control memory address register, and a microinstruction register that holds a microinstruction that is the output of this control memory, and a microinstruction register that decodes the microinstruction. a decoder;
A mapping array control register whose contents can be rewritten by microinstructions and whose output is input to the mapping array, the output of the mapping array,
A read gate circuit for reading by a microinstruction, a general-purpose register that is subject to general microinstruction logic operations, a logic operator, a control line sent from the decoder to the mapping control register, and the read A control line sent to the gate, the general-purpose register, a control unit sent to the logic operation unit, at least the mapping control register, the read gate, the general-purpose register, the logic operation unit, and the microinstruction. It is a microprocessor that has a microprogram control unit with one internal bus that serves as a path for data transfer with registers.

Effect of the present invention With the above-described configuration, the state of the mapping array can be controlled by changing the contents of the mapping array core 1-roll register using microinstructions stored in the control memory, and the state of the mapping array at that time can be controlled. By directly reading the state of the array to the read gate, the operation of the mapping array can be easily and efficiently verified using the microinstructions themselves.

Embodiment FIG. 1 shows a configuration diagram of a microprocessor having a microprogram control section in an embodiment of the present invention. In FIG. 1, a 1-digit machine language instruction register, 2
is a mapping array that decodes the contents of machine language instruction register 1, 3 is a control memory address register that holds the output of mapping array 2, 4 is a control memory that stores a microprogram, and 5 is a control memory that stores the output of control memory 4. 6 is an input/output multiplexer that controls data transfer between an external device and the internal register of the microprocessor; 7 is a decoder that decodes the contents of the microinstruction register 5; 8 is a controller that controls the mapping array 2; 9 is a read gate for a microinstruction to read the output of the mapping array 2, 1Q is a general-purpose register, 11 is a logic operation unit, 200
201.202, 203.204 are control lines 300 sent from the decoder 7 to the mapping control register 8K, lJ-gate 9, control storage address register 3, general-purpose register, and logic operator 11, respectively.
is a bus that serves as a transfer route for internal data of the microprocessor.

The operation of the microprocessor having the microprogram control section of this embodiment configured as described above will be described below.

Regarding machine language instructions prepared for verifying the state of the mapping array, a process for realizing the machine language instructions will be described.

When a machine language instruction is prepared in the instruction register 1 by the input/output multiplexer 6, its interpretation is executed according to the timing chart shown in FIG. The ○ numbers in FIG. 2 correspond to the explanation numbers below.

(2) A machine language instruction prepared in the instruction register (IR) 1 is decoded by the mapping array 2 after a specified timing, and the result is latched in the control address register (CMAR) 3. In Figure 2, the control address register (C
The value n is stored in MAR)3.

(2) The control memory 4 is accessed according to the contents n of the control address register (CMAR) 3, and a microinstruction - is stored in the microinstruction register (MIR) 5 after a predetermined time.

■ The microinstruction In is decoded by the decoder 7.

At this time, it is assumed that the microinstruction in is an instruction to emit data to the mapping array control register (MCTL) aK. Upon execution of the microinstruction -, data ````'' is stored in the mapping control register (MCTL) by the action of the control line 200.

At this time, the control storage address register (CMAR) 3 is updated to n+1 by the action of the control signal 202 from the decoder 7.

■ A microinstruction is received from the control memory 4 according to the contents of the control memory address register (CHAR) 3.

is stored in the microinstruction register (MIR) 5.

Microinstruction 'n+1 is a microinstruction that transfers the current state of mapping array 2 to the intended general purpose register.

By executing the microinstruction 'n+1, the control lines 210, 203, and 204 from the decoder 7 change to the transfer sequence N.
The read gate (MRG) 9 is activated in accordance with the input signal, and the general-purpose register (GR) is
10, the state of the mapping array is transferred through the internal bus 300. In FIG. 2, b is transferred.

As described above, according to the present invention, by using the control register 8 for controlling the state of the mapping array 2 and the read gate 9 for reading the resulting state,
The state of the mapping array 2 can be controlled and the result can be read out, and the operation of the mapping array 12 can be efficiently verified at the same timing as the actual decoding processing timing.

In the embodiment, the data transfer to the mapping register 8 is performed using an emmit instruction, but it goes without saying that a simple transfer instruction may be used.

DETAILED DESCRIPTION OF THE INVENTION As described in detail, according to the present invention, special functions such as serial input/output data transfer for testing purposes are performed in the verification of a mapping array that decodes machine language instructions, which is the central function of a microprocessor having a microprogram control unit. By preparing general hardware based on microinstructions without providing hardware to implement a control mechanism, mapping arrays can be verified quickly and efficiently, which has a great practical effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a microprocessor having a microprogram control section according to an embodiment of the present invention, FIG. 2 is a timing chart explaining the operation of the same embodiment, and FIG. 3 is a conventional microprogram control section. FIG. 2 is a configuration diagram of a microprocessor having the following. 1... Machine language instruction register, 2... Mapping array, 3... Control memory address register, 4... Control memory, 5... ... Marocro instruction register, 6 ... Input/output multiplexer, 7 ... Decoder, 8 ... Mapping control register, 9 ... Read gate,
10... General purpose register, 11... Logical operation unit, 100, 101, 102... Serial input/output data path, 200, 201.202, 203-...
...Control line, 300...Internal bus. Name of agent: Patent attorney Toshio Nakao and 1 other person11
E1 leap 4, ku ot(-1 ~ 螠蓼

Claims (1)

[Claims] An instruction register that stores machine language instructions, a mapping array that takes the output of this instruction register as input and outputs decoding information of the machine language instructions, a control storage address register that holds the output of this mapping array, and this control storage address register. a control memory that stores a microprogram that is accessed by the contents of the control memory, a microinstruction register that holds microinstructions that are the output of this control memory, and a microinstruction register whose contents can be rewritten by the microinstructions and whose outputs are input to the mapping array. A mapping array control register, a read gate for the microinstruction to read the output of the mapping array, a general-purpose register that is the target of the microinstruction's logic operations, an arithmetic unit that performs the logic operations, and a decipherer for decoding the contents of the microinstruction register. a decoder, each independent control line sent from the decoder to the mapping control register, the read gate, the general-purpose register, and the arithmetic unit, and at least the mapping control register;
A microprocessor having a microprogram control section, characterized in that it is provided with one internal bus serving as a route for data transfer between the output of the read gate, the general-purpose register, the arithmetic unit, and the microinstruction register.