JPS5914060A - Switching circuit of memory bank - Google Patents

Abstract

PURPOSE:To switch a memory bank easily, by calling a program of another memory bank to switch the memory bank automatically. CONSTITUTION:When a subroutine call instruction detecting circuit 3 detects a subroutine call instruction from a data bus 5, an FF6 is set up. A call address lower latch 7 executes latch operation, an FF8 is set up. When the call address of the subroutine is latched, a bank address detecting circuit 10 detects whether the call address is included between ''0000'' and ''003F'' or not. When the subroutine call instruction is executed, a CPU saves the returned address from the subroutine in the stack area of a memory. When a subroutine return instruction is executed, the CPU reads out the return address of the subroutine from the stack area of the memory.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory bank switching circuit for switching a plurality of memory banks connected to a CPU.

Generally, in a program storage type computer, the program data to be executed by the CPU is stored in advance in the ROM or memory such as triRA, M, and the initial value of the program code inside the CPU is set as the execution start address. Then, the CPU sequentially counts up the addresses in the program register, reads the instructions stored in the addresses stored in the program register into the CPU, and executes each command one after another. Constructed to go.

However, the size of the memory space that can be directly accessed by the CPU is only 64 bytes from the 0000 address to the FF FF address in the case of an 8-bit CPU, which means that a large amount of data or ':5o crumbs cannot be stored simultaneously. When it is necessary to read data from the KCPU, there is a problem that there is a shortage of memory space. Therefore, conventional methods have been used to connect multiple metrics to the CPU and to switch between them as appropriate.
A method of expanding the space is being developed.

Figure 1 shows such a conventional metering system. It shows I's work. In the figure, fl+ indicates the first memory bank, (2j indicates the second memory bank, and 6 memory banks from address 0000 to F F F'
It has a byte size of 4. However, the part corresponding to the common area (for one person) of the first memory bank fi+ is an empty area (for two people) in the second memory bank f21. However, to explain the operation of the conventional example shown in FIG. When you want to do this, first move the control to the common area (for one person) and move the control to the memory bank (
The bank address is switched from 1) to metric backup (2), and the bank address is switched from common area (IA) to metric backup (2).
2) Call ``jo crum 2.'' This jo jiram 2
When the processing is completed, control returns to the common area (IA), and after switching the bank address from memory address (2) to memory address (1), the process returns to "jOjiraml".Fig. In the conventional example, since the above-mentioned procedure is required, it is necessary to provide a common area (for one person) containing a program for switching bank addresses. The operation is complicated, and the area where the common area (IA) and the address are 1 is occupied by other meters (21 is an empty area (2 people), so the efficiency of using the meter space is said to be poor. There was a problem.

The present invention has been made to solve these problems of the conventional example, and automatically switches the meter by checking the "jO crumb" of the other meter. It is an object of the present invention to provide a multi-bank switching circuit which achieves the following advantages.

The configuration of the present invention will be described below with reference to illustrated embodiments. Second
The figure shows the overall configuration of a micro cosciputer system using the memory bank switching circuit of the present invention. In the same figure, ■) is the CPU, (C) is the ROM, and (6) is the I1.
0 hoard, (6) is an external device.

The CPU (B) and each peripheral device are connected via the space bus, the data bus (5), and the computer bus (1'0).
) is a bank address line for switching. FIG. 3 shows a block diagram of the memory bank switching circuit (8). In the figure, (3j is a subroutine call instruction detection circuit, (4) is a retardancy instruction detection circuit,
The detection operation is performed when the MI multiplied signal H is output when the CPU (B) reads an instruction from the MET. First, subroutine call instruction detection circuit (3)
When detecting a blue routine call instruction from the data bus (5), flip float ff +81 is set and its output Q becomes H. Next, the CPU (B) reads the lower part of the call address of the Riz routine from the memory, so this memory read signal and the flip are 0 to 5 (61
The lower call address is input from the data bus (6+) to the lower call address latch (7) at the timing when both the Q outputs of ; is set, and its output Q becomes H. Therefore, when the CPU (B) reads the upper part of the call address of the command routine from Met, the memory read signal and the Q of the flip-flop (7) Since both outputs are H, the upper part of the call address is input from the data bus (5) to the upper call address latch (9).At this time, the lower call address latch (7) has already written the data. Therefore, no latch operation is performed. When the latch operation of the call address upper latch (9) is completed, both the latches 52, 61, and 8 are set, and their outputs Q become L.

When the call address of the call routine is latched, the bank address detection circuit (10) detects whether the call address is between address 0000 and address 003F.
When an address between the 000 address and the 003F strip is detected, it is latched to the lower 3 addresses of the call address or the bank address latch (1) and becomes a new bank address.
It is output to bank address line 081. As a result, one of the bank addresses from bank address 0 to bank address 7 is selected. At this time, the previous bank address is saved in the bank address latch 02).

By the way, when the CPU () executes a subroutine call instruction, it saves the return address from the routine to the stack area of MET, so the MET'J5 point is H and the puncture address is detected. When the detection output Q of the circuit (lO5) is H, the stack address applied on the address bus (131) is latched into the stack address latch 04. Meanwhile, the CPU (B) executes the return command of the Suzu routine. When executed, the return address of the tab routine is read from the next area, so the return instruction detection circuit (when the detection output of 4 is H and the memory return signal is H) cibalator Qfi+
is enabled and compares the address on the address bus (13+) with the stack address latched in stack address latch 04. If they match, the output of the koshihalator θ clause becomes H, and the bank address latch 0
The original bank address saved in 2) is transferred to the bank address latch (+r), thereby returning to the original bank address. Further, if the comparison result by the cossiparator (05) does not match, the output of the cossiparator (16) becomes L, and the bank attribution is not switched. Note that when the CPU (B) is interrupted or reset, the data in the bank address latch (1) is forcibly reset to 0 through the OR circuit (1141) and initialized to bank address 0. be.

Figure 4 shows the switching operation of the menu according to the present invention.
When bank address 0) is called, bank address 00
Execute from the 0th place, when the 1st place is called, bank att and execute from the 1st place of the second line, and in the same way, when the 7th place is called, bank att and execute from the 7th place of the second place. It is something to do. The same is true when the 3F landing spot is called from the 8th spot, and when the 8th spot is called, execution is performed from the 8th strip of bank address 0, and the 3F landing is]
- When the process is executed, the process is executed starting from the puncture address 703F. From these execution start addresses, it is possible to perform absolute programming to any address within the memory.

FIG. 5 shows an example of the external connection terminals of the CPU (B). In the case of an 8-hit CPU, there are 8 data terminals connected to the data bus (J), ~D7, and the address bus (I3). 16 address terminals Ao”A+ connected to
In addition to s, it is provided with various control terminals connected to the control bus θη, and input terminals y for power supply terminals VDD%GND and oIν. Among the control terminals connected to the control bus 0, MI is the terminal that outputs 1 when the CPU (B) fetches an instruction from the MET, and the above-mentioned operation code fetch signal is output from this terminal MI. It is something that will be done. When the CPU (B) accesses the data, MREQ is
-1) These are terminals that output 1 when accessing 11104-to (D). Also, RD is CPU (6)
WR is a terminal that outputs 1 when the CPU (B) writes data to the memory or I10 board when reading data from the memory or I10 board. RF
SH is a terminal for determining the shift rate of the tie-in RAM. Next, HALT uses CPU (B
) is the terminal that outputs 1 when executing the 0 crumb stop command, and WAIT is the terminal that outputs 1 when the CPU (B)
This is a terminal for inputting signal 1 which causes the execution of Jiram to wait temporarily. Furthermore, INT and NMI are input terminals for interrupts, and BUSRQ and BUSAK are input terminals for CP.
This is an input/output terminal for bus control of U (B).

The present invention is configured as described above, and when the address of the resource bank is within a predetermined range, the puncture address of the memory bank is Since output is made to the line, memory banks can be switched simply by calling the ``JO crumb of another memory bank as a routine from any memory bank, and therefore the operation of switching banks is simple. It has the advantage of being easy to use, and since it does not require a free area unlike the conventional method, it has the advantage of increasing the efficiency of memory space usage.Furthermore, in the present invention, when changing a puncture address, η A stack address latch is provided to save and store the return address of the routine, and the address value on the address bus and the stripe 199 when a return instruction is executed are provided.
Since the puncture address is returned to its original value when it matches the memory contents of the address latch, you can freely use the system call and return commands in the new memory bank of the address latch, and also use the tab routine call. When the number of instructions is one more than the number of return instructions, the puncture address is automatically restored to the original memory address, so the operation is extremely easy.

[Brief explanation of drawings]

Figure 1 is an explanatory diagram of the operation of a conventional memory bank switching circuit, Figure 2 is a professional diagram of an embodiment of the present invention, Figure 3 is a diagram showing the main parts of the same as above, and Figure 4 is the operation of the same as above. The explanatory diagram, FIG. 5, is a diagram showing an example of the arrangement of external connection terminals of the CPU used in the above. @ is CPU, (Mo) to (M7) are memory banks, (3) Harizuruchi, 7] - Le instruction detection circuit, (4
) is a return instruction detection circuit, fil +91 is a latch,
(101 is the basic address rooting circuit, (121 is the bank address latch%, 03r is the address bus, (in Japan is the stack address latch, α6) is the comparator, and θ~ is the puncture address line. Agent: Patent attorney Stone 1) Long 7 bar) Ri0 1 2
3 Atoshisu. ↓ 1 2A
Day to II 12 3 4 Figure 4 5 6 7 1111-・

Claims (1)

[Claims] (A plurality of metrebasics connected redundantly to the same address space accessed by the II CPU, and detection circuits for the first and fourth JPJ2 that respectively detect subroutine call instructions and retardancy instructions among the instructions executed by the CPU) , a latch means that is activated by the output of the first detection circuit and latches the call address of the subroutine; and a third latch means that generates a bank address detection output when the call address latched by the latch means is within a predetermined range. a detection circuit;
A first bank address latch that latches the lower address of the call address and outputs it to the bank address line of the seventh bank during the detection operation of the third detection circuit; A stack address latch that latches the address of the stack chain chain that saves and stores the return address from the address bus, and compares the address value on the address bus and the stored contents of the stack address latch during the detection operation of the second detection circuit. During the detection operation of the cossiparator and the third detection circuit, the data before updating of the first bank address latch is transferred and stored in advance, and the transferred and stored data is transferred to the first bank address latch when the cossiparator outputs a coincidence. A memory bank switching circuit comprising a second bank address latch.