JP3088285B2 - In-circuit emulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an in-circuit emulator, and more particularly to an in-circuit emulator for debugging microcomputer software.

[0002]

2. Description of the Related Art Conventionally, an in-circuit emulator has been widely used as a debugging tool for microcomputer applied equipment. The in-circuit emulator is a device for efficiently debugging an application program created by a user, and can replace the user system and execute the application program in real time (this state is called emulation). After execution, the emulation is temporarily suspended (this state is called a break), and has a function of displaying the register contents at that time, a function of displaying and rewriting the contents of the memory and the registers, and the like.

However, some processing in the user program must be executed periodically even during a break, via an external terminal or in response to a request from other hardware. These processes are described as interrupt processes in the user program. Accordingly, there is an increasing demand for an in-circuit emulator capable of executing a user interrupt during a break, which accepts and executes only the user interrupt process even during a break, and returns to the break state again when the interrupt process ends. On the other hand, several realization methods have been conventionally studied.

First, referring to FIGS. 6A and 6B showing a block diagram of a general conventional first in-circuit emulator which cannot execute a user interrupt during a break, FIG. The in-circuit emulator of
A control unit 1 controls the entire emulation process and interfaces with a host machine (not shown) such as a personal computer for operation by an operator, and an emulation unit 2 executes emulation.

The emulation unit 2 operates in the same manner as the microcomputer to be emulated, and includes an emulation chip 3 (hereinafter referred to as an “evaluation chip”) 31 for executing a debugging function of the emulator.
, An alternate memory 21 storing an execution program of the evaluation chip 31, an emulation memory 22 storing a program to be debugged, and an emulation circuit 3, which is arranged between the alternate memory 21 and the emulation memory 22, for emulating these memories. And a mapper circuit 4 for selecting where to place the address space in the CPU address space.

The mapper circuit 4 includes a mapping register 4
1, 42, address comparators 43 and 44, and an inverter 45.

Next, the operation of the first conventional in-circuit emulator will be described with reference to FIG. 6. The evaluation chip 31 of the emulation circuit 3 is generated in the emulation circuit 3 based on a command from the control unit 1. In response to the supply of the control signal SVI, the supervisor (S
V) Generate a mode signal SVM. The SV mode signal SVM is a special interrupt for emulator control or debugging, that is, a privilege (supervisor) interrupt (hereinafter referred to as SV
I) is a signal indicating that the interrupt has been accepted and the interrupt processing is being performed. EVA chip 31 and alternate memory 2
1, each of the emulation memories 22 is connected via a mapper circuit 4 to an address bus and a data bus.

The emulation memory 22 stores a program to be debugged which the user is trying to debug, and in a normal execution state, that is, a run state, the evaluation chip 31 selects this memory, reads out its contents, and executes it. On the other hand, the alternate memory 21 stores an emulator execution program for executing a debugging function as a so-called emulator system such as causing the evaluation chip 31 to dump its contents in a break state. The evaluation chip 31 enters a break state in response to the supply of the control signal SVI, selects the alternate memory 21 in response to the supply of the SV signal SVM, and executes a program therein.

The comparator 43 of the mapper circuit 4 receives the supply of the SV mode signal SVM as a control input, compares the value of the mapping register 41 with the upper part of the address A of the instruction fetch of the evaluation chip 31, and when they match, the chip select signal CS1 Is output. For example, if the address is 24, 10 is input from the upper side. The chip select signal CS1 generated as a result of the comparison is supplied to the chip select terminal CS of the alternate memory 21. The SV mode signal SVM is inverted by the inverter 45 and supplied to the control input of the comparator 44. The comparator 44 outputs a chip select signal CS <b> 2 when the value of the mapping register 42 matches the comparison result of the higher order of the address A, and supplies the chip select signal CS <b> 2 to the chip select terminal CS of the emulation memory 22. Each of the alternate memory 21 and the emulation memory 22 stores an instruction fetch address A and a data
D is supplied.

The evaluation chip 31 of the emulation circuit 3
Directly outputs the normally used internal SV mode signal as the SV mode signal SVM to the outside. When the SV mode signal SVM is invalid, that is, 0, the address comparator 43 is invalid and its output CS1 is 0, and the alternate memory 21
Do not select On the other hand, the inverter 45 inverts the SV mode signal SVM and activates the address comparator 44. As a result, the set value of the mapping register 42 is compared with the upper value of the address A, and if they match, the chip select signal CS2
Changes to 1 to select the emulation memory 22. Conversely, when the SV mode signal SVM is 1, similarly, the alternate memory 21 corresponds to the set value of the register 41.
Select Therefore, an actual memory is selected based on the control by the SV mode signal SVM and the mismatch between the values of the registers 41 and 42. In some cases, a plurality of such registers and address comparators are provided.

In the first conventional in-circuit emulator, since the SV mode signal SVM is always 1 during a break, the interrupt prohibition circuit 313 operates to accept a user's interrupt request even if it is issued. Can not.

JP-A-1-184545 (Reference 1)
The second conventional in-circuit emulator capable of executing a user interrupt during a break described above is provided with a user interrupt function by a special operation in an evaluation chip of an emulation circuit, which is a main part of executing emulation, thereby providing a user interrupt during a break. Execution of interrupt was enabled.

Referring to FIGS. 7 (A) and 7 (B), which show a second conventional in-circuit emulator in common with FIG. The difference between the conventional second in-circuit emulator and the conventional first in-circuit emulator is that the internal SV mode signal is enabled / disabled by a user operation to enable a user interrupt instead of the emulation unit 2. An emulation section 2A including an emulation circuit 3A having an evaluation chip 300 for setting and generating an external output SV mode signal SVM is provided.

The emulation circuit 3A has a first
Although the same mapper circuit 4 as the conventional circuit is provided, it is not shown for convenience of explanation.

The evaluation chip 300, which is characterized by the second conventional in-circuit emulator, includes a register 311 for setting one of the modes of enabling / disabling interrupt processing during a supervisor mode described later; F that outputs the interrupt mode signal when an interrupt other than
F312, and an interrupt prohibition circuit 313 that prohibits an interrupt in response to the supply of a signal value of 1.

Next, the operation of the second conventional in-circuit emulator will be described with reference to FIG. 7. Similar to the first in-circuit emulator, the alternate memory 21 of the emulation section 2A stores the emulation in the chip select CS. The circuit is supplied with a supervisor (SV) mode signal SVM from the circuit 3A. on the other hand,
The emulation memory 22 receives an inverted SV signal SVMB, which is an inverted signal of the SV mode signal SVM, for the chip select CSB. The evaluation chip 300 receives the supply of the control signal SVI generated in the emulation circuit 3, and the address bus and the data between the evaluation chip 300 and each of the alternate memory 21 and the emulation memory 22 via a mapper circuit (not shown). It is connected by a bus.

In a normal execution state, that is, a run state, the evaluation chip 300 selects the emulation memory 22, reads out the contents thereof, and executes the same as in the first conventional in-circuit emulator. The evaluation chip 300 enters a break state in response to the supply of the control signal SVI, selects the alternate memory 21 in response to the supply of the SV signal SVM, and executes a program therein.

Up to this point, the function is the same as that of the first conventional in-circuit emulator.
1, the emulation 22 and the special evaluation chip 30 as described above with respect to the SV signal SVM.
0 is used. That is, the evaluation chip 300 outputs the internal SV mode signal SVM0 indicating the internal run and break to the outside of the chip as it is,
When the special mode is set in the register 311 instead of supplying the signals to the FF 312 and the FF 312 during the interrupt, the FF 312 is reset during the interrupt. The mode signal SVM0 is not reflected. At the same time, the internal SV mode signal SV
Even if M0 is valid, other interrupts are not prohibited.

[0019] Accordingly, even effective SVI in other words the internal SV mode signal SVM0 becomes possible to accept a user interrupt, that is, the signal R E TI until this interrupt processing is completed is entered when the Until then, the evaluation chip 300 selects an emulation memory as a memory and executes a user interrupt process.

However, the second conventional in-circuit emulator proposes a special evaluation chip as described above in order to be able to accept a user interrupt request during a break. The above function can be realized for a microcomputer having such an evaluation chip prepared.However, for a microcomputer having an evaluation chip, it is necessary to make a new evaluation chip. There is a problem that a new investment on the order of yen is required.

Further, the user needs to purchase a different emulator for each use of a different microcomputer, and also needs to master different usages in accordance with the use. Therefore, it is desired to use a common emulator. Also,
This is also a problem in the development and manufacturing of the emulator supplier, and is also a factor in promoting commonality.

The first problem concerning the common use of emulators is the difference between microcomputers, which cannot be avoided. Therefore, it is possible to consider an emulator in which the control unit 1, the emulation memory 22, the alternate memory 21, the mapper circuit 4, and the like in the first conventional in-circuit emulator are common. The emulation circuit 3 basically depends on the microcomputer to be emulated, but the functions such as a tracer function and a condition break used for debugging can be shared. What remains at the end is the emulation function of the chip function itself, mainly the evaluation chip. Therefore, it is possible to achieve common by independent board so as to be replaceable by extracting the part.

The second problem relates to the control of the run and break of the chip. As in the second conventional in-circuit emulator, it can be controlled to output the corresponding VS mode signal in the chip to the outside. What is different is that although the user interrupt during the break is accepted, the microcomputers of other evaluation chips cannot accept the user interrupt during the break, but the functions are different even though they are common emulators. In addition, despite the fact that an evaluation chip already exists (all existing microcomputers apply), it is costly and time-consuming to newly develop a special evaluation chip such as the second conventional in-circuit emulator for all the microcomputers. Is virtually impossible. However, this type of function is increasingly desired in the future.

Next, a third conventional in-circuit emulator capable of executing a user interrupt during a break described in Japanese Patent Application Laid-Open No. 1-309138 (Document 2) is a special in-circuit emulator such as the second conventional in-circuit emulator. By using an existing chip without using a simple evaluation chip and arranging and using a program used for debugging on the emulation memory used by the user without performing any special operation for memory switching, user interrupts during breaks can be prevented. Execution was possible.

Referring to FIG. 8, which schematically shows the state of the memory space of the emulation memory 22A of the third conventional in-circuit emulator, the emulation memory 22 of the second conventional in-circuit emulator is shown.
A stores a user program 101 and a debugging program 102.

Normally, the user program 101 is executed, and the control is transferred to the debug program 102 by an interrupt corresponding to SVI or data transfer of the data area, and executed. Thus, the user program 10
1 is stopped and the state of execution of the debugging program 102 is a break state. Therefore, in this break state, since the memory is not switched and the state is not the SVI state, if a user interrupt occurs, the user program 101 can be executed again until the interruption ends.

However, since the emulation memory 22A corresponds to the memory of the microcomputer to be emulated, that is, the user memory, the emulation memory 22A uses the capacity of the user memory for the debug program 102. Will not be able to use the maximum memory capacity.

[0028]

The above-mentioned first in-circuit emulator of the prior art has a drawback that the interrupt prohibition circuit operates during a break so that even if there is a user interrupt request, it cannot be accepted. was there.

The conventional second in-circuit emulator which can accept a user interrupt request during a break requires a special evaluation chip for supervisor signal processing, and has a drawback that it becomes a hindrance to the common emulator. Was. Further, an evaluation chip including such a special function newly requires a large amount of development cost and man-hour, and has a disadvantage that it is practically impossible to newly develop an existing microcomputer.

In the third conventional in-circuit emulator that can accept a user interrupt request during a break by using an existing evaluation chip, a debug program is arranged on the user's program memory, so that the program area to be executed by the user is The disadvantage is that the user cannot utilize the maximum memory capacity of the microcomputer.

An object of the present invention is to make it possible to accept a user interrupt request during a break, to eliminate the need for a special evaluation chip relating to supervisory signal processing, to realize a common emulator, and to use a user memory area. It is to provide an in-circuit emulator that is unnecessary.

[0032]

An in-circuit emulator according to the present invention comprises a control section for controlling the entire emulation processing, and an evariance chip for performing the same operation as the microcomputer to be emulated and executing the debugging function of the emulator. An emulation circuit that includes an emulation circuit that includes a debug program for executing the evolution chip, an emulation memory that stores a user program to be debugged, and executes an emulation. An emulator control privilege interrupt is generated for the emulation unit, and the emulation unit switches the emulation memory to the alternate memory in response to the generation of the privilege interrupt. In in-circuit emulator for executing ® down, the emulation circuit is set in response to execution of said debug program includes a mode flag circuit generating a resettable mode flag, the alternate notes and the emulation circuit
Memory and the emulation memory.
These memories are emulated by the microcomputer
And where to place it in the address space of the
Wherein in a range of addresses that are present in the alternate memory in the privileged interrupt and when the set of mode flags selected otherwise the alternate memory is provided with a mapper circuit for selecting said emulation memory, responsive to said privileged interrupts The low-priority interrupt can be accepted when a low-priority interrupt having a priority equal to or lower than the privileged interrupt occurs even in a break state in which the execution of the user program is interrupted. It is.

[0033]

Next, an embodiment of the present invention will be described with reference to FIG.
1 (A) and 1 (B), which are denoted by common reference characters / numerals and are similarly indicated by blocks,
The in-circuit emulator of the present embodiment shown in this figure has a control unit 1 common to the first example of the prior art and an emulation unit 2B having a user interrupt reception function during a break.
And

The emulation section 2B includes an alternate memory 21 common to the conventional one and an emulation memory 2
2 and an emulation circuit 3B having a common evaluation chip 31 and a mode flag circuit 32 for generating a mode flag F whose value can be rewritten by executing an instruction of the evaluation chip 31, and a mapping register 41 common to the conventional technology. , 42 and the address comparators 43, 44,
An OR gate 46 for taking a logical sum of the SV mode signal SVM and the mode flag F and supplying this logical sum signal OV to the control input of the address comparator 43;
Alternatively and an inverter 47 for supplying inverted and the chip sensor recto signal CS1 output to the control input of the address comparator 44 the address comparator 43, Supabai
During interrupt interrupt (SVI) and when mode flag F is set
This alteration is performed using the existence range address of the tonate memory 21.
Select emulator memory 21 and emulation otherwise
A mapper circuit 4A for selecting the memory 22 is provided.

Next, the operation of this embodiment will be described with reference to FIG. 1. First, like the first conventional in-circuit emulator, the evaluation chip 31 of the emulation circuit 3B has a supervisor interrupt (SVI). The internal SV signal SVM signal is output to the outside as it is as the supervisor (SV) mode signal SVM indicating that the reception / interruption processing is being performed. The mode flag F generated by the mode flag circuit 32 is supplied to the OR gate 46 of the mapper circuit 4A. The OR gate 46 receives the supply of the mode flag F and the SV mode signal SVM to generate a logical sum signal O.
V is supplied to the control input of the address comparator 43.

The comparator 43 receives the supply of the logical sum OV at the control input, and outputs the same to the mapping register 4 as in the prior art.
1 is compared with the high order address A of the instruction fetch of the evaluation chip 31, and when they match, the chip select signal CS1
And supplies it to the chip select terminal CS of the alternate memory 21. The inverter 47 inverts the chip select signal CS1 and supplies the inverted signal to the control input of the address comparator 44. The comparator 44 outputs a chip select signal CS <b> 2 when the value of the mapping register 42 matches the comparison result of the higher order of the address A, and supplies the chip select signal CS <b> 2 to the chip select terminal CS of the emulation memory 22.
Each of the alternate memory 21 and the emulation memory 22 receives an instruction fetch address A and data.

First, the SV signal SVM is 0, and the mode flag F generated by the mode flag circuit 32 is also 0.
Then, the OR signal OV output from the OR gate 46 also becomes 0 in response to the respective values 0 of the signal SVM and the flag F, and the output chip select signal CS1 becomes 0 in the inactive state of the address comparator 43. . Therefore, the alternate memory 21 is not selected. On the other hand, the inverter 47 inverts the value 0 of the chip select signal CS1 and outputs 1 as the value of the signal IV. In response to the value 1 of the signal IV, the address comparator 44 becomes active and the set value of the mapping register 42 at that time and the address A
Is compared with the upper value of the chip select signal CS
2 changes to 1 to select the emulation memory 22.

Next, when the SV signal SVM is 1, or when the mode flag F is 1, these signals SVM,
The output OR signal OV of the OR gate 46 also becomes 1 in response to any value 1 of the flag F, the address comparator 43 becomes active, and the chip select signal CS1 is set to 1 in accordance with the set value of the register 41. The alternate memory 21 is selected. When the alternate memory 21 is selected, the emulation memory 22 is not selected, but when the alternate memory 21 is not selected, the emulation memory 22 is selected according to the value of the mapping register 42.

Next, referring to FIG. 2A which is a flowchart showing a procedure for shifting from the run state to the break state of the in-circuit emulator of the present embodiment,
First, in the run state (step S1), the SV signal SVM
Is 0 and the mode flag F is also set to the initial value 0, as described above, the alternate memory 21 is in the non-selected state, and selects the emulation memory 22 only in the address range set by the mapping register 42. Therefore, the program on the emulation memory 22 is normally executed as long as the user's program runs in the mapped range.

Here, when an SVI occurs to set a break state, the SV signal SVM becomes 1 as described above.
The alternate memory 21 is selected in the address range set by the mapping register 41 (step S2). In the program on the alternate memory 21, the mode flag F is rewritten to 1, the return address of the user program and other information are saved, the return address is set to the subsequent program address for debugging, and the return SVI is executed. (Step S3).

Then, the SV signal SVM becomes 0, but since the mode flag F is 1, the mapping register 41
As long as there is control of the program in the address range set in step (1), the alternate memory 21 is preferentially selected and its contents are executed. In this state, if there is an interrupt request from the user, this interrupt request is accepted because the SV signal SV is 0 (step S4). As a result, by setting the vector address and the interrupt processing program so that they do not overlap with the alternate memory 21, the emulation memory 22 is enabled in the mapping range of the alternate memory 21 outside the mapping range. Therefore, the user interrupt routine on the emulation memory 22 is executed. When the execution of the interrupt processing is completed, the execution program moves to the alternate memory 21 again.

Referring to FIG. 3, which schematically shows the memory state during this transition, the emulation memory 22 during the run.
During the break, the selection of the alternate memory 21 has priority, and the emulation memory 22 is also accessible at the same time.

Also, in the present embodiment, it can be seen that the number of circuits actually added is small compared to the conventional first in-circuit emulator. That is, the circuit of this embodiment can be realized by changing a part of the mapper circuit.

Also, in the case where the conventional evaluation chip 300 with the special function of the second circuit is used in place of the evaluation chip 31 of the present embodiment, the evaluation chip 31 and the function of the evaluation chip 300 which use the special function described above must be activated. Can be used as well. When the special function is used, the operation of the conventional second circuit can be realized unless the mode flag F is operated without using the processing procedure of the present embodiment. Therefore, the in-circuit emulator of the present embodiment can realize commonality without depending on the evaluation chip.

Next, referring to FIG. 2B which is a flowchart showing the procedure for shifting from the break state to the run state, first, in the break state (step S5), the SV signal SVM once responding to the occurrence of SVI after a 1 state, the processing procedure of processing the opposite break from the run, i.e. switch to alternate memory of the memory (step S6), and sets and mode flag reset information of the return destination, etc. of the saving user program and return execution of SVI (step S7), the and the run-shaped on purpose made by continued execution of the user program (step S8).

Next, FIGS. 4A and 4B show the second embodiment of the present invention in the same manner as in FIG. For reference, the difference between this embodiment and the first embodiment is as follows.
The emulation unit 2C of the present embodiment replaces the inverter 47 with the SV signal SVM and the chip select signal CS.
That is, a mapper circuit 4B having a NOR gate 48 which takes a NOR (NOR) with 1 and generates a NOR signal NV is provided.

Next, the operation of the present embodiment will be described with reference to FIG. 4. First, as in the first embodiment, the evaluation chip 31 responds to the occurrence of SVI as the SV mode signal SVM. An SV signal SVM is output. The mode flag F is supplied to the OR gate 46 of the mapper circuit 4A. The OR gate 46 receives the supply of the mode flag F and the SV mode signal SVM to generate a logical sum signal OV.
Is supplied to the control input of the address comparator 43.

The comparator 43 receives the supply of the logical sum OV at the control input, and outputs a chip select signal CS1 corresponding to the result of the comparison between the value of the mapping register 41 and the upper address A of the instruction fetch of the evaluation chip 31. Chip select terminals CS and NO of alternate memory 21
To the R gate 48.

The NOR gate 48 takes the NOR of the SV signal SVM and the chip select signal CS1 and takes the NOR signal NV.
To the control input of the address comparator 44.
When the NOR signal NV is 1, the comparator 44 outputs the chip select signal CS2 when the comparison result between the value of the mapping register 42 and the higher order of the address A matches, and supplies the chip select signal CS2 to the chip select terminal CS of the emulation memory 22. Each of the alternate memory 21 and the emulation memory 22 receives an instruction fetch address A and data.

First, when both the SV signal SVM and the mode flag F are 0, the OR signal OV of the OR gate 46 is responsive to the value 0 of each of the signal SVM and the flag F.
Is also 0, and the chip select signal CS1 output from the address comparator 43 is also 0, so that the alternate memory 21 is not selected. On the other hand, the NOR gate 48 outputs the signal NV having the value 1 in response to the value 0 of the signals SVM and CS1. In response to the value 1 of the signal NV, the address comparator 44 becomes active, and selects the emulation memory 22 in accordance with the coincidence of the comparison result between the set value of the mapping register 42 and the upper value of the address A at that time.

Next, when the SV signal SVM is 1, the output OR signal OV of the OR gate 46 also becomes 1 regardless of the value of the mode flag F, and the value of the output signal NV of the NOR gate 48 becomes 0. Therefore, the alternate memory 21 is selected according to the value of the mapping register 41, and the emulation memory 22 is not selected.

When the mode flag F is 1 and the signal SVM is 0, the output OR signal OV of the OR gate 46 becomes 1
And the address comparator 43 becomes active,
The chip select signal C corresponding to the set value of the register 41
The alternate memory 21 is selected by setting S1 to 1. When the alternate memory 21 is in the selected state, the NOR gate 48 becomes 0 and the emulation memory 22 is not selected. Address comparator 43 because of mismatch with register 41
Is 0, the address comparator 44 is activated, so that the emulation memory 22 is selected according to the value of the mapping register 42.

Next, referring to FIG. 2A again and FIG. 5 schematically showing the memory state of the present embodiment, the transition from the run state to the break state of the in-circuit emulator of the present embodiment will be described. First, in the run state (step S1), assuming that the values of the SV signal SVM and the mode flag F are 0, the alternate memory 2
1 is a non-selection state, and selects the emulation memory 22 only in the address range set by the mapping register 42. Therefore, the program on the emulation memory 22 is normally executed as long as the user's program runs in the mapped range.

Here, when an SVI is generated to set a break state, the SV signal SVM becomes 1, and as described above,
The alternate memory 21 is selected in the address range set by the mapping register 41 (step S2). At this time, unlike the first embodiment, the emulation memory 22 cannot be selected regardless of the value of the mode flag F. Referring to FIG. 5, this state is changed from the valid state (A) of the emulation memory 22 to the alternate memory 21.
In the valid state (B). Next, in the program on the alternate memory 21, the mode flag F
To 1 to save the restoring address of the user program and other information, set the restoring address to the subsequent program address for debugging, and execute the return SVI (step S3).

Then, the SV signal SVM becomes 0, but since the mode flag F is 1, the mapping register 41
As long as there is control of the program in the address range set in step (1), the alternate memory 21 is preferentially selected and its contents are executed. In this state, if there is an interrupt request from the user, this interrupt request is accepted because the SV signal SV is 0 (step S4). By setting the relationship between the vector address, the interrupt processing program, and the alternate memory in the same manner as in the first embodiment, the emulation memory 22 is located outside the mapping range of the alternate memory 21.
Activates in the mapping range. Therefore, the user interrupt routine on the emulation memory 22 is executed. When the execution of the interrupt processing is completed, the execution program moves to the alternate memory 21 again.

At this time, as shown in FIG. 5C, during the break, selection of the alternate memory 21 has priority and the emulation memory 22 can be accessed at the same time.

[0057]

As described above, according to the present invention, in-circuit emulator according to the present invention, the emulation circuit comprises a set corresponding to the execution of the debugging program, the mode flag circuit generating a resettable mode flag, et
Simulation circuit and alternate memory and emulation
These memories are located between the
Of the address space of the microcomputer to be
Where select alternate memory at a predetermined address range in the time set in the privileged interrupt and the mode flag with select whether to place comprising a mapper circuit for selecting an emulation memory for the rest, the user split even when a break state By accepting
There is no need to develop a special evaluation chip for enabling the acceptance of a user interrupt during a break, and it is possible to eliminate a factor that causes a large amount of cost and man-hour.

In addition, it is easy to absorb the difference between the evaluation chips with respect to the requirement of accepting the above-mentioned user interrupt, which is one of the hindrance factors, in response to the demand for a common emulator corresponding to different microcomputers for each user. There is an effect that the emulator can be shared.

Further, there is an effect that the user can use the maximum memory capacity of the microcomputer to be emulated without reducing the program memory of the user for realizing the function of enabling the acceptance of the user interrupt. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of an in-circuit emulator according to the present invention.

FIG. 2 is a flowchart illustrating an example of an operation of the in-circuit emulator according to the present embodiment.

FIG. 3 is a schematic diagram illustrating an example of a memory state in the in-circuit emulator according to the present embodiment;

FIG. 4 is a block diagram showing a second embodiment of the in-circuit emulator according to the present invention.

FIG. 5 is a schematic diagram illustrating an example of a memory state in the in-circuit emulator according to the present embodiment;

FIG. 6 is a block diagram showing an example of a first conventional in-circuit emulator.

FIG. 7 is a block diagram showing an example of a second conventional in-circuit emulator.

FIG. 8 is a schematic diagram showing an example of a memory state in a third conventional in-circuit emulator.

[Explanation of symbols]

 Reference Signs List 1 control unit 2, 2A, 2B, 2C emulation unit 3, 3A, 3B emulation circuit 4, 4A, 4B mapper circuit 21 alternate memory 22 emulation memory 31, 300 evaluation chip 32 mode flag circuit 41, 42 mapping register 43, 44 address comparison Circuits 45, 47 Inverter 46 OR gate 48 NOR gate 311 Register 312 Flip-flop 313 Interrupt inhibit circuit

Continuation of front page (56) References JP-A-1-184545 (JP, A) JP-A-4-139538 (JP, A) JP-A-61-45338 (JP, A) JP-A-61-177552 (JP, A) , A) (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 11/22-11/34

Claims (4)

(57) [Claims] An emulation circuit including an emulation chip for performing the same operation as a microcomputer to be emulated and executing a debug function of an emulator, and a control unit for controlling the entire emulation processing. An emulation unit having an alternate memory storing a debug program of the above and an emulation memory storing a user program to be debugged, and performing an emulation, wherein the control unit interrupts the emulation unit with a privilege interrupt for controlling an emulator. Wherein the emulation unit switches the emulation memory to the alternate memory in response to the generation of the privileged interrupt, and executes the emulation. Serial emulation circuit, set to correspond to the execution of said debug program includes a mode flag circuit generating a resettable mode flag, the alternate memory Contact with the emulation circuit
And between the emulation memory and
Memory of the microcomputer to be emulated
A mapper circuit that selects where in the address space to place the memory and selects the alternate memory with an address in the range where the alternate memory is present during the privileged interrupt and when the mode flag is set, and otherwise selects the emulation memory. Receiving a low-priority interrupt when a low-priority interrupt having a priority equal to or lower than the privileged interrupt occurs even in a break state in which execution of the user program is interrupted in response to the privileged interrupt. An in-circuit emulator characterized in that: 2. The system according to claim 1, wherein said mapper circuit is activated in response to supply of a first address control signal and first and second registers respectively setting first and second address values. A first address comparing circuit for outputting a first match signal for selecting the alternate memory in response to a match between the address value of the address bus and the upper bit value of the address bus; and supplying a first address control signal. A second address comparing circuit which is activated in response to the second address value and outputs a second match signal for selecting the emulation memory in response to a match between the comparison result of the second address value and the upper bit value of the address bus. The in-circuit emulator according to claim 2, comprising: 3. A first logic gate for performing a logical operation of the low-priority interrupt-corresponding interrupt mode signal and the mode flag to generate the first address control signal; 3. The in-circuit emulator according to claim 1, further comprising an inverter circuit that inverts a first coincidence signal to generate the second address control signal. 4. A first logic gate circuit for performing a logical operation on the low-priority interrupt-corresponding interrupt mode signal and the mode flag to generate the first address control signal; claim 1 or, characterized in that it comprises a second logic gate circuit for generating the second address control signal performs a logical operation between the said interrupt mode signal first coincidence signal
2. The in-circuit emulator according to 2 .