JPH02130040U - - Google Patents
Info
- Publication number
- JPH02130040U JPH02130040U JP3690889U JP3690889U JPH02130040U JP H02130040 U JPH02130040 U JP H02130040U JP 3690889 U JP3690889 U JP 3690889U JP 3690889 U JP3690889 U JP 3690889U JP H02130040 U JPH02130040 U JP H02130040U
- Authority
- JP
- Japan
- Prior art keywords
- address
- microprogram
- stores
- central processing
- section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005856 abnormality Effects 0.000 claims 2
- 238000000034 method Methods 0.000 claims 1
- 230000000717 retained effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Description
第1図はこの考案の一実施例による計算機を示
す構成図、第2図はこの考案の計算機におけるマ
イクロプログラムの処理シーケンスのフローチヤ
ート、第3図は従来の計算機の構成図、第4図は
従来の計算機におけるマイクロプログラムの処理
シーケンスのフローチヤートである。
図において、1……主記憶部、2……マイクロ
ROM部、3……中央演算処理部、4……マツプ
ROM部、5……セレクタ、6……アドレスカウ
ンタ、7……マイクロ履歴RAM部である。なお
、図中、同一あるいは相当部分には、同一符号を
付して示してある。
Fig. 1 is a block diagram showing a computer according to an embodiment of this invention, Fig. 2 is a flowchart of a microprogram processing sequence in the computer of this invention, Fig. 3 is a block diagram of a conventional computer, and Fig. 4 is a block diagram showing a computer according to an embodiment of this invention. 1 is a flowchart of a microprogram processing sequence in a conventional computer. In the figure, 1...Main storage unit, 2...Micro ROM unit, 3...Central processing unit, 4...Map ROM unit, 5...Selector, 6...Address counter, 7...Micro history RAM unit It is. In the drawings, the same or corresponding parts are designated by the same reference numerals.
Claims (1)
主記憶部と、上記主記憶部より呼び出された命令
を実行し、演算能力を持つている中央演算処理部
と、その中央演算処理部に対して処理シーケンス
を収納してあるマイクロ固定記憶処理部と、上記
マイクロ固定記憶装置部に対して、その命令の処
理すべきマイクロプログラムの開始が収納されて
いるマツプ固定記憶部と、上記中央演算処理の演
算結果又は上記マツプ固定記憶装置部の出力した
開始アドレスかを選択するセレクタとを備えた計
算機において、上記マツプ固定記憶装置の開始ア
ドレスをアクセスしたと同時に絶えず最小アドレ
スから最大アドルスを示すアドレスカウンタと、
このアドレスカウンタの示しているアドレスに上
記開始アドレスそのものを書き込むことができ、
上記マイクロプログラムの処理シーケンスに異常
が発生した場合、異常発生までのマイクロプログ
ラムの処理シーケンスを命令のマイクロプログラ
ムの実行アドレス毎に履歴として保持する手段と
を具備したことを特徴とする計算機。 A main memory section that stores a program that performs a predetermined job, a central processing section that executes instructions called from the main memory section and has arithmetic capabilities, and a central processing section that performs processing for the central processing section. A micro-fixed memory processing unit that stores sequences, a map-fixed memory unit that stores the start of a microprogram to process the instruction for the micro-fixed memory unit, and a central processing unit that stores the instructions. an address counter that constantly indicates from the minimum address to the maximum address at the same time as the start address of the map fixed storage device is accessed;
The above starting address itself can be written to the address indicated by this address counter,
A computer characterized by comprising: when an abnormality occurs in the processing sequence of the microprogram, the processing sequence of the microprogram up to the occurrence of the abnormality is retained as a history for each execution address of the microprogram of instructions.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3690889U JPH02130040U (en) | 1989-03-30 | 1989-03-30 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3690889U JPH02130040U (en) | 1989-03-30 | 1989-03-30 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02130040U true JPH02130040U (en) | 1990-10-26 |
Family
ID=31543553
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3690889U Pending JPH02130040U (en) | 1989-03-30 | 1989-03-30 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02130040U (en) |
-
1989
- 1989-03-30 JP JP3690889U patent/JPH02130040U/ja active Pending
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