JPH02226429A - Information processor - Google Patents

Abstract

PURPOSE:To reduce the switching steps of a task and to make an overhead to minimum by switching respective tasks based on a task switching instruction at the time of executing a multi-task processing. CONSTITUTION:When the state of a new task (state is mentioned as a resuming address here) is stored in a certain address in a storage part 4, the address is set to be an operand and an EXC instruction is executed among old tasks. Then, the next instruction of the EXC instruction, namely, the state of the old task (resuming address of the old task) is stored in the designated operand. At the same time, the original value of the operand (the resuming address of the new task) is stored in a program counter 3, and the execution of the program is resumed from the address. Thus, the switching of the task is executed. Since the task processing is executed by directly designating the address of the memory, the content of the program counter 3 can respectively be preserved and called by one step.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to an information processing device that performs multitask processing.

(Prior Art) A task, which is a unit of work from the perspective of a central processing unit, basically transits through three states, namely, a running state, a ready state, and a waiting state, from its creation until its disappearance. In addition to this, special states include tasks being created and tasks disappearing.

In multitasking, the task management program
It selects and starts the one with the highest execution priority among the ready and deaf tasks, and also performs synchronization and execution control between tasks.

By the way, in conventional multitasking processing, task control blocks (hereinafter referred to as TCBs) that save the task state are combined for each task, and only one selected TCB is enabled to execute the task. A control method is used to control the state.

A program that performs such processing is called a multitasking operating system (O8).

However, when switching tasks, switching between 1IE1'cB and the new TCB is required, which requires at least several steps of processing. For this reason, the overhead of 181 times of calculation time spent by each program of O8 was not negligible.

(Problems to be Solved by the Invention) As described above, in the conventional multitasking processing described above, overhead is wasted.

The present invention was made in view of the above circumstances, and an object of the present invention is to provide an information processing apparatus that can minimize overhead.

[Structure of the Invention] (Means for Solving the Problem) In order to achieve the above object, the information processing device of the present invention has the following features:
In an information processing apparatus that executes multitasking processing, the information processing apparatus includes an address storage means for storing an address of an execution instruction and a processing procedure storage means for storing a processing procedure. It is provided with a task switching instruction for exchanging respective data with the storage means, and switching between each task is performed based on this task switching instruction when executing multitasking processing.

(Function) The information processing device of the present invention is provided with a task switching instruction for exchanging data between the address storage means and the processing procedure storage means, so that task switching can be performed when executing multitasking processing. Each task can be switched based on a command, thereby reducing the number of task switching steps.

(Example) Hereinafter, details of an example of the present invention will be described based on the drawings.

FIG. 1 shows an embodiment in which the information processing apparatus of the present invention is applied to an electronic computer.

As shown in the figure, the electronic computer includes an arithmetic control section 2, a program counter 3, and a storage section 4 connected via an internal bus 1.

The arithmetic control unit 2 applies certain processing to an operand specifying an object to be arithmetic, and obtains a result.

The program counter 3 is a register that stores the address of the next instruction to be executed.

The storage unit 4 stores programs for processing procedures.

This electronic computer is equipped with a task switching instruction (EXC) which is an instruction to exchange one operand with the address of the program counter 3 and the contents of the operand.

Then, when the state of the new task (here, the state refers to the restart address of the task) is stored at a certain address in the storage unit 4, the address is set as an operand and 1[
] When an EXC instruction is executed from within a task, the next instruction after the ExC instruction, that is, the state of the old task (11
1 open address) is stored in the specified operand.

At the same time, the original value of the operand (the restart address of the new task) is stored in the program counter 3, and execution of the program starts +1r from that address. Task switching is performed in this way.

Next, the operation of the computer according to the present invention will be explained using FIGS. 2 to 5.

First, the initial settings of multitasking O8 are executed (step 2
01), the execution start addresses of tasks A, B, and C are stored in Sa, Sb, and Se, respectively (step 20).
2) To be done.

Next item, step 203, EXCSa, EX
Tasks A, B, and C are switched by sequentially executing Csb and PIXCSc.

In other words, when EXCSa is executed, the process is executed as task A.
Move to. When EXCSa is executed (step 302) after Pal is executed in task A (step 301), the process returns to step 203, where EXCsb is executed, so the process moves to task B.

In task B, after pbi is executed (step 401), EXCSb is executed (step 402), the process returns to step 203, and EXCSc is called here, so the process moves to task C.

In task C, after Pel, Pc2, and Pc3 are executed in this order (steps 501 to 503), EXC
When Sc is executed (step 504), step 20
Since EXCSa in 3 is executed, the process shifts to task A again.

In task A, after Pa2 and Pal are executed in this order (step 303) and (step 301), EXC
9a is executed (step 302), step 20
Since EXCSb in task B is executed, the process moves to task B again.

In task B, after Pb2 is executed (step 403), l:Xc Sb is executed (step 404), and EXCSc in step 203 is executed, so the process shifts to task C again.

In task C, Pcl, Pc2, Pc3,
EXCSa executes in this order (steps 501 to 504)
be done.

In this way, tasks A, B, and C are executed alternately.

In this way, in this embodiment, task processing is performed by directly specifying the memory address, so the contents of the program counter 3 can be saved and recalled in one step, thereby reducing overhead. Can be done.

6 to 9 show the task switching command EXC mentioned above.
In place of the above, another embodiment is shown in which an instruction EXCn(r) which specifies a memory whose address is the sum of a constant n and the contents of a register r is applied.

First, initial settings for multitasking O3 (step 601)
After this is performed, the execution start addresses of tasks A, B, and C are stored after Sa (step 602). Then r
After ←−1 is executed (step 603), r −(r
+1) By executing sod3 and EXC5a(r) (step 604), tasks A, B, and C are switched.

That is, r4- (r+1)rAod3, EX
When C5a(r) is executed, the process moves to task A. After Pal is executed in task A (step 701), r
” (r+1)a+od3 When EXC5a(r) is executed (step 702), the process moves to task B.

In task B, after Pbl is executed (step 801), r = (r+1)Ilod3, EXC5a(
r) is executed (step 802), the process moves to task C.

In task C, after Pet, Pc2, and Pc3 are executed in this order (steps 901 to 903), r-(
When EXC5a(r) is executed (step 904), the process returns to step 604,
Here, “←(r+1)mod3, EXC5a(r)
is executed, the process shifts to task A again.

In task A, after Pa2 and Pal are executed in this order (step 703) and (step 701), r-(
r+l)mod3, EXC5a(r) is executed (step 702), the process shifts to task B again.

In task B, after Pb2 is executed (step 803), r − (r + l) mod 3, EXC5a (r)
is executed (step 804), the process moves to task C again.

In task C, after Pcl, Pc2, and Pc3 are executed in this order (steps 901 to 903), r4
- (r+l)n+od3 When EXC5a(r) is executed (step 904), the process moves to step 604 in the same manner as described above.

In this way, tasks A, B, and C are executed alternately.

Thus, in this example, tasks A and B.

Since the multitask O8 does not intervene when switching the processing in CIHI and intervenes only when switching from task C to task A, the overhead can be further reduced.

In each of the embodiments described above, the instruction IEXc for exchanging the contents of the program counter 3 and the operand, and the instruction EXCn(r) for specifying the memory whose address is the sum of the constant n and the contents of the register r are applied. , but this example is not limited to the instruction EXC@m that specifies a memory whose address is the contents of memory m, the instruction EXCr that specifies register r, and the instruction EXC@ that specifies a memory whose address is the contents of register ``. r etc. may be applied.

[Effects of the Invention As explained above, according to the information processing device of the present invention,
Since each task can be switched based on a task switching instruction when performing multitasking processing, the number of task switching steps can be reduced, and thereby overhead can be kept to a minimum.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the information processing apparatus of the present invention applied to a computer, and FIGS. 2 to 5 show the operation of the computer shown in FIG. 1 when it is equipped with an EXC instruction. The flowcharts shown in FIGS. 6 to 9 show other embodiments of the present invention, in which the electronic computer in FIG.
(r) It is a flowchart which shows the operation|movement when a command is provided. 1...Internal bus, 2...Arithmetic control unit, 3...Program counter, 4...Storage unit Applicant: Toshiba Corporation

Claims (1)

[Claims] (1) In an information processing device that executes multitasking processing, the information processing device includes an address storage unit that stores an address of an execution instruction, and a processing procedure storage unit that stores a processing procedure, wherein the information processing device A task switching instruction is provided for exchanging data between the storage means and the processing procedure storage means, and each task is switched based on this task switching instruction when executing multitasking processing. An information processing device characterized by: