JPH04346136A - Virtual instruction processor structure control method - Google Patents

Abstract

PURPOSE:To provide the virtual instruction processor structure control method capable of arbitrarily changing the processing ability of a data processing system by changing the system structure during the operation of the operating system in a computer system. CONSTITUTION:A computer system, equipped with physical instruction processors 1 and 2 for an physical computer 9 and a virtual instruction processor to be used by logically dividing the physical instruction processors 1 and 2, corresponds to one or more tasks 14, 15, 18, and 19 realizing the virtual instruction processor for each physical instruction processor 1 and 2. By the generation and deletion of the task, the number of virtual instruction processors is increased or reduced, so as to perform the control setting the allocation of the virtual instruction processor to physical instruction processors and the number of virtual instruction processors.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a virtual instruction processor configuration control method, and more particularly to a virtual instruction processor that has a plurality of physical instruction processors of a physical computer and uses the plurality of physical instruction processors by logically dividing them. In a computer system equipped with, changing the configuration of a virtual instruction processor,
The present invention relates to a virtual instruction processor configuration control method that performs configuration control such as reconfiguration.

0002

2. Description of the Related Art Conventionally, in order to provide appropriate services in response to many data processing requests from a plurality of users, a data processing system is operated under the control of an operating system. In order to ensure that a hardware computer system that runs an operating system has sufficient data processing capacity necessary for system operation, the storage capacity of the storage device to be built into the system, the number of instruction processors, etc. are determined, and the system configuration is performed. The data processing system is operated accordingly.

[0003] In such a data processing system,
In order to operate the system appropriately and to increase the data processing capacity in the future, the processing capacity of the system, such as the storage capacity of the storage device built into the system and the number of instruction processors, can be arbitrarily changed. It is desirable to be able to change the configuration arbitrarily.

However, in the past, the system configuration has been changed statically, but not dynamically. As a technique for changing the system configuration to increase this kind of data processing capacity, for example, Japanese Patent Application Laid-Open No. 63-1639
In the proposal for a "processor expansion system" described in Publication No. 53, an electronic exchange (data processing system) can be configured from a uniprocessor configuration to a multiprocessor configuration in order to minimize call processing (data processing service) interruption time. In order to migrate to , store the expanded system file in a part of the external storage device in advance, switch the connection between the communication path system and processor, and start up the system with the expanded system file. We are adding more processors for call processing.

As described above, when reconfiguring the instruction processor in a computer system, it is necessary to stop and restart the system. In addition, even when operating a system that implements a virtual computer system under the control of an operating system, when reconfiguring the instruction processor, stop the operating system of the relevant virtual computer system, and then stop the logical partition. , the configuration of the corresponding virtual instruction processor is changed.

[0006]

[Problems to be Solved by the Invention] As described above, in the conventional technology, when changing the built-in configuration of an instruction processor in a computer system, consideration is given to dynamically changing (reconfiguring) the system configuration. has not been done. For example, if an attempt is made to change the system configuration while an operating system is being operated on a virtual computer system, the operating system and logical partition must be terminated. However, during operation of the operating system,
The process of terminating the operating system and logical partitions places a heavy load on the operating system, making it virtually impossible to dynamically change the system configuration.

The present invention provides a computer system having a plurality of physical instruction processors of a physical computer and a virtual instruction processor that logically divides and uses the plurality of physical instruction processors, even during operation of an operating system. It is an object of the present invention to provide a virtual instruction processor configuration control method that allows the processing capacity of a data processing system to be arbitrarily changed by changing the system configuration and enables effective system operation.

[0008]

[Means for Solving the Problems] In order to achieve the above object, the virtual instruction processor configuration control method of the present invention has a plurality of physical instruction processors of a physical computer, and logically divides the plurality of physical instruction processors. In a computer system equipped with virtual instruction processors used as virtual instruction processors, the number of virtual instruction processors can be increased or decreased by associating one or more tasks that implement virtual instruction processors with each physical instruction processor, and creating and erasing the tasks. do,
It is characterized by performing configuration control for allocating virtual instruction processors to a plurality of physical instruction processors and setting the number of virtual instruction processors.

[0009]

According to the virtual instruction processor configuration control method of the present invention, tasks are created and deleted while the logical partition and operating system are being executed. The task here is to realize a virtual instruction processor.
One or more tasks are associated with each physical instruction processor. The virtual instruction processor operates as if an instruction processor existed due to the operation of the task, so the creation and deletion of the task has the same effect as connecting or disconnecting the virtual instruction processor in the virtual computer system. Become. This allows dynamic reconfiguration control of the virtual instruction processor.

[0010] By controlling the system configuration in this manner, the system configuration can be dynamically changed, and when a system is operated using virtual computer system technology, processing performance can be dynamically optimized during system operation.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating the configuration of a computer system according to an embodiment of the present invention in relation to a physical computer and a virtual machine. FIG. 1 shows the assignment of tasks in a virtual computer system to physical instruction processors in a physical computer. In FIG. 1, 1 is a first instruction processor (physical instruction processor), and 2 is a second instruction processor (physical instruction processor). Each of the first instruction processor 1 and the second instruction processor 2 internally holds numbers #1 and #2, respectively. 3 is a console, and 4 is a common memory. The common memory 4 is accessible from both the first instruction processor 1 and the second instruction processor 2. The console 3 is a display input/output device that serves as a user interface between the operator and the virtual machine 10.

The virtual computer 10 includes a first instruction processor 1 (instruction processor #1) which is a physical instruction processor.
Monitor task 11 and frame task 12 running on
Then, logical partition (LPAR#1) task 13 is generated. Similarly, the first physical instruction processor
A virtual instruction processor (LIP#1.1) that operates on the instruction processor 1 (instruction processor #1) of , and operates under the control of the logical partition (LPAR#1) task 13.
A task 14 is generated and the system is operated. In addition, if necessary, as will be described later, a virtual instruction processor (LIP#2) that operates under the control of a logical partition (LPAR#2) task 17 that operates on the second instruction processor 2 (instruction processor #2) is added. .1) Task 15 is generated and runs on the first instruction processor 1 (instruction processor #1) of the physical instruction processors;
The system is operated.

Furthermore, a monitor task 16 that operates on the second instruction processor 2 (instruction processor #2), which is a physical instruction processor, and a logical partition (LPAR #2) task 17 are generated in the virtual machine 10. Furthermore, a virtual instruction processor (LIP#2.1) task 18 controlled by the logical partition (LPAR#2) task 17 is generated to operate the system. In addition, if necessary, the above-mentioned logical partition (L
A virtual instruction processor (LIP#1.2) task 19 that operates under the control of the PAR#1) task 13 is newly generated to perform system operation. Note that this virtual instruction processor (LIP#1.2) task 19 is operated in the system as a task that operates on the second instruction processor 2 (instruction processor #2), which is a physical instruction processor.

A physical instruction processor 1 is stored in the common memory 4.
A first task queue 5 (task queue #1) that queues tasks that run on the physical instruction processor 2 (instruction processor #1), and a second task queue that queues tasks that run on the physical instruction processor 2 (instruction processor #2). task queue 6
(task queue #2), and a task queue for queuing tasks that operate on any physical instruction processor of physical instruction processor 1 (instruction processor #1) and physical instruction processor 2 (instruction processor #2). 3 task queues 7 (task queue #3) are provided. In this way, corresponding to each physical instruction processor, each task queue is provided for queuing tasks that operate on the physical instruction processor.

[0015] Here, the second processor, which is a physical instruction processor,
Virtual instruction processor (LIP#1.2) task 1 operating on instruction processor 2 (instruction processor #2) of
By newly generating 9, the logical partition (LP
AR#1) Increase the number of virtual instruction processors controlled by task 13, while increasing the number of virtual instruction processors (L
IP#2.1) By erasing task 15, the first
The number of virtual instruction processors operating on each physical instruction processor is adjusted by reducing the number of virtual instruction processors operating on instruction processor 1 (instruction processor #1). In this way, the physical instruction processor allocation of the virtual instruction processors (virtual instruction processor allocation for each physical instruction processor) is changed, and system reconfiguration processing is performed.

FIG. 2 is a functional block diagram showing the system configuration of a virtual machine. In FIG. 2, 21 is a monitor section, and the monitor section 21 has a task management function, an interrupt handler mechanism, a timer control function, and a macro control function. 23, 24, 27,
28 is a virtual instruction processor section, and these virtual instruction processor (hereinafter abbreviated as LIP) sections have an instruction simulator function and an interrupt simulator function. In addition, 22 and 26 are logical partition sections, and logical partitions (hereinafter referred to as LPAR) are logical partition sections.
) section has a LIP control function that controls the virtual instruction processor.

LI that realizes the functions of a virtual instruction processor
P section 23 (LIP#1.1) and LIP section 24 (LIP#1.2) are controlled by LPAR section 22 (LPAR#1), and LIP section 27 (LIP#2.1) and LIP section 28
(LIP#2.2) is LPAR section 26 (LP
AR#2). One operating system can run in each LPAR. Also,
A frame section 25 has an input/output function for inputting and outputting commands and data from an operator via a console (3; FIG. 1). Since the processing function of each section is executed by task processing, data communication between each section is made possible by using the inter-task communication function to communicate commands and data within the virtual machine.

FIG. 3 is a diagram showing the format of an instruction word for executing instruction processor reconfiguration with a physical computer by the operating system. This command word is
As shown in the figure, it is composed of an opcode 31 and an operand 32. An instruction processor number is set in the operand 32, and processing for executing instruction processor reconfiguration is performed.

FIG. 4 is a flowchart showing the processing flow of a task that implements a virtual instruction processor, and FIG. 5 is a flowchart showing the processing flow of a logical partition task. Further, FIG. 6 is a flowchart showing the processing flow of the macro execution unit of the monitor task. Figures 4 to 6
A specific example of creation and deletion of a LIP task (virtual instruction processor) will be explained with reference to . Generation of LIP task is
This is done by processing a monitor task using the CRTASK macro issued by LPAR. Also, to delete the LIP task,
This is realized by the DETASK macro issued by LPAR.

First, referring to FIG. 5, in the processing of the logical partition task, as shown in FIG. , in the next step 52, generate all LIPs by CRTASK. Thereafter, in step 53, instructions from other tasks are awaited.

Each LI realizing a virtual instruction processor
The processing of the P task is executed according to the processing flow shown in FIG. The processing of the LIP task is started by the CRTASK of the LPAR task and by the processing of the macro execution unit as shown in FIG.

The LIP task processing will be explained with reference to FIG. 4. In the LIP task processing, in step 40, LIP startup processing is performed, and then in step 41, the task startup of the operating system is performed. The operating system runs. For example, when the operating system receives a command to reconfigure the instruction processor using an instruction word as shown in FIG. 3, it stores the instruction processor number as an operand and executes the instruction word using an opcode that distinguishes the operation (connection or disconnection). . The command word also automatically becomes a command word simulation request by LIP, and the processing here is controlled from step 41 to step 4.
I will move on to 2. In step 42, in order to guarantee the operation of the operating system, physical registers,
Information such as the program status word is saved to memory. Then, in the next step 43, it is determined whether the command to be executed in this task is another simulation request command or the relevant reconnection command for system configuration control. That is, in step 43,
It is determined whether the operation code is an LIP generation or deletion instruction. If the operation code is an LIP generation or deletion instruction, the process proceeds to step 44, where the instruction processor number is notified to the LPAR (LPAR task) and generation/deletion (of the LIP) is instructed. This notifies the LPAR task of an instruction processor number and a connection (meaning task creation) or disconnection (meaning task deletion) instruction through inter-task communication. On the other hand, if the opcode is not an LIP generation or deletion instruction, it is another simulation request instruction, and the process proceeds to step 45, where another instruction simulation process related to the instruction word is performed. Then, the process proceeds to step 46.

[0023] The LPAR processing will be described later, but the LPAR
In response to the completion notification from , the LIP task performs recovery processing of the previously saved information (operating system task information) in the next step 46 . Then, the process returns to step 41 and the operating system task is started again.

Continuing the explanation with reference to FIG. 5 again, in step 53, when the LPAR task in the WAIT state receives communication from the frame task or the LIP task under its control, it changes from the WAIT state. It will be canceled. Then, in the next step 54, the reconfiguration request is distinguished from other requests, and if it is a reconfiguration request, the next step 5
In step 5, new LIP (task) generation processing and LIP (task) deletion processing are separately performed. That is, in step 54, it is determined whether the request is a reconfiguration request from a LIP (task) or a frame (task), and if it is a reconfiguration request, the process proceeds to step 55, where a new LIP is requested.
Determine whether it is generated. If it is determined that a new LIP is to be generated, in step 56, an instruction processor number (physical instruction processor) that is not used by the LIP task under the control of the LPAR task is determined. Then, in the next step 57, the CRTASK macro is processed,
Generates a LIP (task). If the reconfiguration request is determined not to generate a new LIP in the determination process of step 55, the reconfiguration request is a request to delete a LIP task, so the process proceeds to step 58, where the DETASK macro is processed and the corresponding LIP Delete tasks. Then, the process returns to step 53 and enters a WAIT state, in which it waits for communication of a processing request from the next task.

On the other hand, the determination process in step 54 determines that the processing request received from another task through inter-task communication is
If it is determined that the reconfiguration request is not from an IP (task) or a frame (task), the process proceeds to step 59, performs other processing for the corresponding processing request, returns to step 53, enters the WAIT state, It enters a state where it waits for communication of a processing request from the next task.

[0026] To specifically explain the processing of the reconfiguration request here, for example, the LPAR task
AR task 13; Figure 1), LIP #1.2 (
Since the LIP task 19 (Figure 1) has not been generated yet, if the reconfiguration request is a LIP generation request, the instruction processor number #2 of the second instruction processor 2 as the physical instruction processor is obtained, and the operand of the CRTASK task is , the LIP number #1.2 and the instruction processor number #2 are specified, and the LIP number is specified by the process of the monitor task.
An IP task 19 (LIP #1.2) is generated as a virtual instruction processor that operates on the second instruction processor 2 (physical instruction processor with instruction processor number #2). Also, if the reconfiguration request is an LIP deletion request, LPAR
When the task is LPAR #2 (LPAR task 17; Figure 1), if instruction processor number #1 is specified as the operand of the DETASK task, LIP task 15 (LIP #2.1) is deleted by the monitor task processing. be done. In this way, the generation and deletion of LIP tasks are performed, and the reconfiguration control of the virtual instruction processor is performed.

Next, the processing of the macro execution unit of the monitor task will be explained according to the processing flow shown in FIG. When a processing request macro is issued, in step 61 it is determined whether the macro is CRTASK. CRT
If it is determined that the ASK is ASK, the process proceeds to step 62, a task management table is created, and in the next step 63, the task queue (5) corresponding to the instruction processor number of the physical instruction processor specified as an operand is
, 6, 7; Figure 1) to queue the task management table.

On the other hand, if the macro is not determined to be CRTASK in the determination process of step 61, then the process proceeds to step 64, where it is determined whether the macro is DETASK. If it is determined that the task is DETASK, the process proceeds to step 65, and it is determined whether the corresponding task whose deletion is instructed by the operand is being executed. If the task is currently being executed, the task is deleted in the spin loop of step 65. Wait until the end of execution, and when the execution of the task is finished and registered in the task queue for next processing, the task management table is dequeued from the task queue in step 66, and the task management table is dequeued in the next step 67. to erase. Also, in the judgment at step 64, the macro is DETASK.
If it is not determined that this is the case, then the process proceeds to step 68, and the corresponding other process is performed.

In the above description of the embodiment, it was assumed that the virtual machine receives the command from the operating system, but the command is input from the frame task and the LPA
Even if the R task receives it through inter-task communication, Figure 5
Similar processing is performed by the processing shown in FIG.
System reconfiguration control of creation and deletion of virtual instruction processors can be performed.

As described above, according to the virtual instruction processor configuration control method of this embodiment, task generation and deletion are performed in the same way as the startup process of the virtual instruction processor, without terminating the operating system on the virtual machine. , it is possible to perform reconfiguration control of the virtual instruction processor.

[0031]

As described above, according to the present invention, a virtual instruction processor can be reconfigured using a method similar to the start-up process of creating and erasing tasks for realizing a virtual instruction processor. Therefore, the system configuration can be easily reconfigured without increasing the load on the operating system. Furthermore, since reconfiguration processing can be performed without terminating the operating system, processing performance can be dynamically optimized during system operation.

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating the configuration of a computer system according to an embodiment of the present invention in relation to a physical computer and a virtual machine;

[Fig. 2] Fig. 2 is a functional configuration block diagram showing the system configuration of a virtual machine;

FIG. 3 is a diagram showing the format of an instruction word for executing instruction processor reconfiguration with a physical computer by an operating system;

FIG. 4 is a flowchart showing the processing flow of a task to realize a virtual instruction processor;

FIG. 5 is a flowchart showing the processing flow of a logical partition task;

FIG. 6 is a flowchart showing the processing flow of a macro execution unit of a monitor task.

[Explanation of symbols]

1 First instruction processor (physical instruction processor) 2
Second instruction processor (physical instruction processor) 3
Console 4 Shared memory 5, 6, 7 Task queue 9 Physical computer 10 Virtual computer 11, 16 Monitor task 12 Frame task 13, 17 LPAR (logical partition) task 14, 15, 18, 19 LIP (virtual instruction processor) task 21 Monitor Section 22, 26 Logical partition section 23, 2
4, 27, 28 Virtual instruction processor section 31 Opcode 32 Operand

Claims (1)

[Claims] Claim 1: In a computer system including a plurality of physical instruction processors of a physical computer and a virtual instruction processor that logically divides and uses the plurality of physical instruction processors, a virtual instruction processor is realized for each physical instruction processor. assign one or more tasks to a plurality of physical instruction processors, and increase and decrease the number of virtual instruction processors by creating and deleting the tasks, allocating virtual instruction processors to multiple physical instruction processors, and setting the number of virtual instruction processors. A virtual instruction processor configuration control method characterized by performing configuration control.