JPH02119744U - - Google Patents
Info
- Publication number
- JPH02119744U JPH02119744U JP2838689U JP2838689U JPH02119744U JP H02119744 U JPH02119744 U JP H02119744U JP 2838689 U JP2838689 U JP 2838689U JP 2838689 U JP2838689 U JP 2838689U JP H02119744 U JPH02119744 U JP H02119744U
- Authority
- JP
- Japan
- Prior art keywords
- storage unit
- fixed storage
- microprogram
- arithmetic processing
- processing sequence
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002159 abnormal effect Effects 0.000 claims 1
- 230000005856 abnormality Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Description
第1図はこの考案の一実施例による計算機を示
す構成図、第2図はこの考案の計算機におけるマ
イクロプログラムの処理シーケンスのフローチヤ
ート、第3図は従来の計算機の構成図、第4図は
従来の計算機におけるマイクロプログラムの処理
シーケンスのフローチヤートである。
図において、1はマイクロROM部、2は中央
演算処理部、3はマツプROM部、4はセレクタ
、5はカウンタ、6はドライバ、7は表示器であ
る。なお、図中同一あるいは相当部分には同一符
号を付して示してある。
Fig. 1 is a block diagram showing a computer according to an embodiment of this invention, Fig. 2 is a flowchart of a microprogram processing sequence in the computer of this invention, Fig. 3 is a block diagram of a conventional computer, and Fig. 4 is a block diagram showing a computer according to an embodiment of this invention. 1 is a flowchart of a microprogram processing sequence in a conventional computer. In the figure, 1 is a micro ROM section, 2 is a central processing section, 3 is a map ROM section, 4 is a selector, 5 is a counter, 6 is a driver, and 7 is a display. It should be noted that the same or corresponding parts in the drawings are designated by the same reference numerals.
Claims (1)
央演算処理部と、上記演算処理部に対して処理シ
ーケンスを記載したマイクロ固定記憶装置部と、
上記マイクロ固定記憶装置部に対して、その処理
すべきマイクロプログラムの開始アドレスが収納
されているマツプ固定記憶装置部と、上記中央演
算処理部の演算結果か、または上記マツプ固定記
憶装置部の出力した開始アドレスかを選択するセ
レクタとを備えた計算機において、ある所定のマ
イクロステツプ数を設定出来るカウンタとマイク
ロプログラムの処理シーケンスが上記設定マイク
ロステツプ数以上費やした時、異常を表示するた
めのドライバ及び表示器を付加することによつて
、マイクロプログラムの異常処理シーケンスが発
生した場合、外部に表示出来ることを特徴とする
計算機。 a central arithmetic processing unit that executes predetermined instructions and has arithmetic processing capacity; a micro fixed storage unit that stores a processing sequence for the arithmetic processing unit;
For the micro fixed storage unit, there is a map fixed storage unit that stores the start address of the microprogram to be processed, and the calculation result of the central processing unit or the output of the map fixed storage unit. In a computer equipped with a selector for selecting a starting address, a counter that can set a predetermined number of microsteps, and a driver and a driver for displaying an abnormality when the processing sequence of the microprogram takes more than the set number of microsteps. A computer characterized in that by adding a display device, when an abnormal processing sequence of a microprogram occurs, it can be displayed externally.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2838689U JPH02119744U (en) | 1989-03-13 | 1989-03-13 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2838689U JPH02119744U (en) | 1989-03-13 | 1989-03-13 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02119744U true JPH02119744U (en) | 1990-09-27 |
Family
ID=31251710
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2838689U Pending JPH02119744U (en) | 1989-03-13 | 1989-03-13 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02119744U (en) |
-
1989
- 1989-03-13 JP JP2838689U patent/JPH02119744U/ja active Pending
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