JPH0334146U - - Google Patents
Info
- Publication number
- JPH0334146U JPH0334146U JP1989095583U JP9558389U JPH0334146U JP H0334146 U JPH0334146 U JP H0334146U JP 1989095583 U JP1989095583 U JP 1989095583U JP 9558389 U JP9558389 U JP 9558389U JP H0334146 U JPH0334146 U JP H0334146U
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- address
- port
- section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Digital Computer Display Output (AREA)
- Debugging And Monitoring (AREA)
Description
第１図は本考案の一実施例の構成を示すブロツ
ク図、第２図は第２図に示す入出力アクセス情報
表示部１３の一例を示す図である。
１……アドレスバス、２……データバス、３…
…入出力アクセス情報、４……入出力ポートアド
レス情報、５……入力ポートアドレス表示部、６
……入力ポートデータ表示部、７……出力ポート
アドレス表示部、８……出力ポートデータ表示部
、９……出力ポートアクセス実施アドレス表示部
。
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a diagram showing an example of the input/output access information display section 13 shown in FIG. 1...address bus, 2...data bus, 3...
...Input/output access information, 4...Input/output port address information, 5...Input port address display section, 6
...Input port data display section, 7...Output port address display section, 8...Output port data display section, 9...Output port access execution address display section.
Claims (1)
ドレス入力部と、該アドレス入力部からの入出力
アドレス情報を入力しＣＰＵとメモリ間のアドレ
スバスおよびデータバスを常時監視して表示対象
入出力ポートがＣＰＵにてアクセスされた時に入
力ポートアドレスと入力ポートデータまたは出力
ポートアドレスと出力ポートデータと出力ポート
アクセス実施アドレスの５種類の入出力アクセス
情報を検出する入出力アクセス情報検出部と、該
入出力アクセス情報検出部からの前記入出力アク
セス情報を入力し表示する入出力アクセス情報表
示部を有することを特徴とする、マイクロプロセ
ツサの入出力情報表示装置。 There is an address input section for inputting the address of the input/output port to be displayed, and input/output address information from the address input section is input, and the address bus and data bus between the CPU and memory are constantly monitored. an input/output access information detection unit that detects five types of input/output access information: an input port address, input port data, output port address, output port data, and output port access implementation address when accessed by the input/output access; An input/output information display device for a microprocessor, comprising an input/output access information display section that inputs and displays the input/output access information from an information detection section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989095583U JPH0334146U (en) | 1989-08-14 | 1989-08-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989095583U JPH0334146U (en) | 1989-08-14 | 1989-08-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0334146U true JPH0334146U (en) | 1991-04-03 |
Family
ID=31644841
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989095583U Pending JPH0334146U (en) | 1989-08-14 | 1989-08-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0334146U (en) |
-
1989
- 1989-08-14 JP JP1989095583U patent/JPH0334146U/ja active Pending