JPS63107044U - - Google Patents
Info
- Publication number
- JPS63107044U JPS63107044U JP20254786U JP20254786U JPS63107044U JP S63107044 U JPS63107044 U JP S63107044U JP 20254786 U JP20254786 U JP 20254786U JP 20254786 U JP20254786 U JP 20254786U JP S63107044 U JPS63107044 U JP S63107044U
- Authority
- JP
- Japan
- Prior art keywords
- block selection
- memory device
- selection register
- common bus
- bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Devices For Executing Special Programs (AREA)
- Debugging And Monitoring (AREA)
Description
第１図は、本考案の一実施例を示す構成ブロツ
ク図、第２図は、第１図の装置の動作を説明する
フローチヤート、第３図は、従来のソフトウエア
開発支援装置を含むシステムの構成ブロツク図で
ある。
１……ＣＰＵ装置、２……メモリ装置、２１…
…ブロツク選択レジスタ、２２……メモリブロツ
ク制御部、２３……メモリブロツク、３……共通
バス、４……ソフトウエア開発支援装置、４１…
…ブロツク選択情報記憶部、４２……モニター制
御部、４３……トレース部、４４……トリガー部
、５……第２のバス。
FIG. 1 is a configuration block diagram showing an embodiment of the present invention, FIG. 2 is a flowchart explaining the operation of the device shown in FIG. 1, and FIG. 3 is a system including a conventional software development support device. FIG. 1...CPU device, 2...Memory device, 21...
...Block selection register, 22...Memory block control unit, 23...Memory block, 3...Common bus, 4...Software development support device, 41...
...Block selection information storage unit, 42...Monitor control unit, 43...Trace unit, 44...Trigger unit, 5...Second bus.
Claims (1)
らＣＰＵ装置、メモリ装置の間で情報の授受を行
う共通バス、この共通バスに流れるアドレス信号
やデータ信号を監視するソフトウエア開発支援装
置よりなるシステムであつて、 メモリ装置のメモリ空間をブロツク単位で拡張
する場合に当該ブロツクの一つを指定するブロツ
ク選択レジスタ、このブロツク選択レジスタとＣ
ＰＵ装置を接続する第２のバスとを備えるか又は
前記メモリ装置の特定アドレスにこのブロツク選
択レジスタを設けて、ブロツク選択レジスタの内
容を書き替えてアクセスできる空間を拡張したシ
ステムにおいて、 前記第２のバス又は前記特定アドレスへの書き
込み動作をモニターして、メモリ装置内のブロツ
ク選択レジスタに書き込まれるデータを記憶する
ブロツク選択情報記憶部、 前記共通バスのアクセス情報と当該ブロツク選
択情報記憶部の内容を記憶するトレース部、 前記共通バスのアクセス情報と当該ブロツク選
択情報記憶部の内容とを合わせたものと外部より
設定されたアクセス情報とを比較し、一致を判断
するトリガー部、 を具備することを特徴とするソフトウエア開発
支援装置。[Claims for Utility Model Registration] A CPU device, a memory device that stores information, a common bus that exchanges information between the CPU device and the memory device, and software that monitors address signals and data signals flowing through this common bus. A system consisting of a development support device, which includes a block selection register that specifies one of the blocks when expanding the memory space of a memory device in units of blocks, and a block selection register and a C
A second bus for connecting a PU device, or a system in which the block selection register is provided at a specific address of the memory device, and the contents of the block selection register are rewritten to expand the accessible space. a block selection information storage unit that monitors write operations to the bus or the specific address and stores data written to a block selection register in the memory device; access information of the common bus and the contents of the block selection information storage unit; a trace unit that stores the access information of the common bus and the contents of the block selection information storage unit, and a trigger unit that compares the access information set from the outside with the access information set from the outside and determines a match. A software development support device featuring:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986202547U JPH0435956Y2 (en) | 1986-12-25 | 1986-12-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986202547U JPH0435956Y2 (en) | 1986-12-25 | 1986-12-25 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63107044U true JPS63107044U (en) | 1988-07-11 |
| JPH0435956Y2 JPH0435956Y2 (en) | 1992-08-25 |
Family
ID=31167033
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986202547U Expired JPH0435956Y2 (en) | 1986-12-25 | 1986-12-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0435956Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5769343A (en) * | 1980-10-09 | 1982-04-28 | Fujitsu Ltd | Paging system of microcomputer |
| JPS57137951A (en) * | 1981-02-18 | 1982-08-25 | Nec Corp | Data processor |
-
1986
- 1986-12-25 JP JP1986202547U patent/JPH0435956Y2/ja not_active Expired
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5769343A (en) * | 1980-10-09 | 1982-04-28 | Fujitsu Ltd | Paging system of microcomputer |
| JPS57137951A (en) * | 1981-02-18 | 1982-08-25 | Nec Corp | Data processor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0435956Y2 (en) | 1992-08-25 |
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