JPH0435956Y2 - - Google Patents

Description

[Detailed description of the invention] (Field of industrial application) The present invention relates to a memory system that has an expanded space for accessing a software development support device using a common bus, and in particular, the present invention relates to a memory system that has an expanded space for accessing a software development support device using a common bus.
It relates to something that can be identified on the CPU side to facilitate software development.

(Prior Art) FIG. 3 is a block diagram of a system including a conventional software development support device. In the figure, 1 is a CPU device, 2 is a memory device that stores information, 3 is a common bus that exchanges information between the CPU device 1, memory device 2, etc., and 4 is an address signal and data signal flowing through the common bus 3. It is a software development support device that monitors the following information, and is equipped with a trace function that stores this information and a trigger function that determines whether any conditions match.

(Problem to be solved by the invention) In such a device, if the memory space of the memory device 2 is expanded using the value of the block selection register, the CPU device 1
The value of the block selection register is rewritten using a second bus different from the block selection register.

However, in this case, the software development support device 4
can only understand the contents of the common bus 3, so if the CPU device 1 controls the block selection register and accesses the expanded space, the software development support device 4 cannot recognize the block address in some way. However, there was a problem that it could not perform its functions satisfactorily.

The present invention solves these problems and is a software development support device in which the software development support device 4 monitors the contents of the block selection register and obtains all address information along with the contents of the common bus 3. The purpose is to provide

(Means for solving the problem) The present invention that achieves the above purpose consists of a CPU device 1, a memory device 2 for storing information, and a memory device 2 for storing information.
A common bus 3 that exchanges information between the CPU device and the memory device, a block selection register 21 that specifies one of the blocks when expanding the memory space of the memory device in units of blocks, and a connection between this block selection register and the CPU device. A second bus 5 connecting
This is used in a system that allows access to memory space expanded by the number of blocks based on the address information output from the CPU device to a common bus and the contents of the block selection register. The software development support device 4 for monitoring address signals and data signals has the following configuration.

That is, a block selection information storage unit 41 stores data written to the block selection register using the second bus as a monitor, a trace unit 43 stores access information of the common bus and the contents of the block selection information storage unit, a trigger section 44 that compares the combination of the access information of the common bus and the contents of the block selection information storage section with the access information set from the outside and determines a match;
It is characterized by having the following.

(Function) The present invention is directed to a software development support device (debugger) used in a system in which the memory space of a memory device is expanded in units of blocks. The block selection information storage unit monitors the block selection information flowing on the second bus, and stores the same content as the data stored in the block selection register. This eliminates the need to connect a special signal line between the memory device and the software development support device.
This can be done with the existing common bus as well as a second bus. The trace section and trigger section implement the trace function and trigger function of the debugger, and in order to deal with expansion of memory space, determine the contents of the block selection information storage section and the common bus together.

(Example) The present invention will be explained below using the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, parts having the same functions as those in FIG. 3 are given the same reference numerals and their explanations will be omitted. In the figure, 21 is a block selection register that takes in the block selection information flowing to the second bus 5, and 22 is a memory block control unit that selects a memory block 23 based on the block selection information stored in the block selection register 21. A designated address is accessed based on the access information flowing through the common bus 3. 23 is a memory block expanded using block selection information.

41 is a block selection information storage unit that takes in the block selection information flowing on the second bus 5; 42 is a monitor control unit that determines whether the block selection information is a write operation to the block selection register 21;
If it is a write operation, the contents are written to the block selection information storage section. 43 is a trace unit that stores the contents of the common bus 3 and the block selection information storage unit 41; 44 is a unit that compares the combined contents of the common bus 3 and the block selection information storage unit 41 with access information set from the outside. This is the trigger part that determines the match.

The operation of the device configured in this manner will be described next. FIG. 2 is a flowchart illustrating the operation of the apparatus shown in FIG. In the figure, A indicates a CPU device 1, B a memory device 2, and C a software development support device 4.

The CPU device 1 uses the second bus 5 to output block selection information in order to access the memory expansion space (S11).

The memory device 2 takes this value into the block selection register 21 (S21). The memory block control unit 22 switches the memory block 23 to be accessed from the outside according to the value of the block selection register 21 (S22).

The software development support device 4 monitors communication on the second bus 5 (S31). Monitor control unit 4
Step 2 determines whether the content of the communication is a write operation to the block selection register 21 (S32). If it is a write operation, block selection information is written into the block selection information storage section 41 (S33).

Next, the CPU device 1 uses the common bus 3,
Access the memory device 2 (S12).

The memory device 2 is an expanded memory block 23
Allow access to (S23).

The software development support device 4 uses the access information on the common bus 3 and the block selection information stored in the block selection information storage section 41 to operate the trace section 43 and the trigger section 44 (S34).
In this way, the expanded memory block 23
It is also memorized and condition matching judgment is made.

(Effects of the invention) As explained above, the invention has the following effects.

A block selection information storage unit is provided inside the software development support device to monitor block switching in the memory space by intercepting signals flowing to the second bus. It can be handled simply by connecting to the bus, making it easy to connect to the system.

Since block switching in the memory space is monitored by intercepting the signal flowing to the second bus, the CPU device can be reliably stopped at the trigger address even if block switching occurs at high speed.
In addition to time-division use, the debugger function is equally maintained in random switching.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram showing an embodiment of the present invention, FIG. 2 is a flowchart explaining the operation of the device shown in FIG. 1, and FIG. 3 is a system including a conventional software development support device. FIG. 1...CPU device, 2...Memory device, 21...
...Block selection register, 22...Memory block control unit, 23...Memory block, 3...Common bus, 4...Software development support device, 41...
...Block selection information storage unit, 42...Monitor control unit, 43...Trace unit, 44...Trigger unit, 5...Second bus.

Claims (1)

[Claims for Utility Model Registration] CPU device 1, memory device 2 for storing information,
A common bus 3 that exchanges information between the CPU device and the memory device, a block selection register 21 that specifies one of the blocks when expanding the memory space of the memory device in block units, and a block selection register 21 that specifies one of the blocks when expanding the memory space of the memory device in units of blocks. This system is equipped with a second bus 5 for connecting devices, and is used in a system that can access a memory space expanded by the number of blocks based on the address information output from the CPU device to the common bus and the contents of the block selection register. The software development support device 4 that monitors address signals and data signals flowing through the common bus includes a block selection information storage unit that monitors the second bus and stores data written to the block selection register. 41. A trace section 43 that stores the access information of the common bus and the contents of the block selection information storage section; a trace section 43 that stores the access information of the common bus and the contents of the block selection information storage section; A software development support device comprising: a trigger unit 44 that compares the access information obtained with the access information obtained and determines a match.