JPS61204257U - - Google Patents

Info

Publication number
JPS61204257U
JPS61204257U JP8867085U JP8867085U JPS61204257U JP S61204257 U JPS61204257 U JP S61204257U JP 8867085 U JP8867085 U JP 8867085U JP 8867085 U JP8867085 U JP 8867085U JP S61204257 U JPS61204257 U JP S61204257U
Authority
JP
Japan
Prior art keywords
address
storage areas
setting
selection means
microprogram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8867085U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8867085U priority Critical patent/JPS61204257U/ja
Publication of JPS61204257U publication Critical patent/JPS61204257U/ja
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例の回路構成を示す
ブロツク図である。 11……通常処理用ROM、「7」……共有領
域、「7′」……試験用プログラム領域、12…
…テスト用回路、13……アドレス用ラツチ回路
、14……デコーダ、15,16……アンド回路
、17……テスト入力端子、18……インバータ
、19……ワイヤード・オア回路。
FIG. 1 is a block diagram showing the circuit configuration of one embodiment of this invention. 11... ROM for normal processing, "7"... Shared area, "7'"... Test program area, 12...
... Test circuit, 13 ... Address latch circuit, 14 ... Decoder, 15, 16 ... AND circuit, 17 ... Test input terminal, 18 ... Inverter, 19 ... Wired OR circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 1チツプのLSIで構成されるマイクロプロセ
ツサにおいて、通常の処理プログラムとテストプ
ログラムとを別々のアドレス空間となる記憶領域
に分離して設定させる設定手段と、上記通常の処
理プログラム及びテストプログラムのいずれかの
実行を選択する選択手段と、この選択手段に応じ
て上記分離された記憶領域いずれかのアドレス制
御を行なうアドレス制御手段とを具備したことを
特徴とするマイクロプログラム制御による電子機
器。
In a microprocessor configured with a one-chip LSI, a setting means for separating and setting a normal processing program and a test program in storage areas serving as separate address spaces; 1. An electronic device controlled by a microprogram, comprising: selection means for selecting execution; and address control means for controlling the address of one of the separated storage areas in accordance with the selection means.
JP8867085U 1985-06-12 1985-06-12 Pending JPS61204257U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8867085U JPS61204257U (en) 1985-06-12 1985-06-12

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8867085U JPS61204257U (en) 1985-06-12 1985-06-12

Publications (1)

Publication Number Publication Date
JPS61204257U true JPS61204257U (en) 1986-12-23

Family

ID=30642027

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8867085U Pending JPS61204257U (en) 1985-06-12 1985-06-12

Country Status (1)

Country Link
JP (1) JPS61204257U (en)

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