JPS61189345U - - Google Patents

Info

Publication number
JPS61189345U
JPS61189345U JP7176185U JP7176185U JPS61189345U JP S61189345 U JPS61189345 U JP S61189345U JP 7176185 U JP7176185 U JP 7176185U JP 7176185 U JP7176185 U JP 7176185U JP S61189345 U JPS61189345 U JP S61189345U
Authority
JP
Japan
Prior art keywords
stack
ram
address
counter
microprogram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7176185U
Other languages
Japanese (ja)
Other versions
JPH0418043Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7176185U priority Critical patent/JPH0418043Y2/ja
Publication of JPS61189345U publication Critical patent/JPS61189345U/ja
Application granted granted Critical
Publication of JPH0418043Y2 publication Critical patent/JPH0418043Y2/ja
Expired legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

図面はこの考案の一実施例を示すもので、第1
図は回路構成を示すブロツク図、第2図は第1図
の切替用RAMの構成を象徴する図である。 11……ROM、111……デコーダ、12,
17,21……セレクタ、13……共用RAM、
14……制御部、15……切替用RAM、16…
…アドレスラツチ回路、17……セレクタ、18
……演算部、19……スタツクカウンタ、20…
…スタツク用RAM、21……セレクタ、X0,
X1,X2,X3,X4……レジスタ。
The drawing shows one embodiment of this invention.
The figure is a block diagram showing the circuit configuration, and FIG. 2 is a diagram symbolically showing the configuration of the switching RAM shown in FIG. 1. 11...ROM, 111...decoder, 12,
17, 21...Selector, 13...Shared RAM,
14...control unit, 15...switching RAM, 16...
...Address latch circuit, 17...Selector, 18
...Arithmetic unit, 19...Stack counter, 20...
...RAM for stack, 21...Selector, X0,
X1, X2, X3, X4...Register.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] サブルーチンのリターンアドレスを順次記憶す
るスタツクRAMと、このスタツクRAMのアド
レスを指定するスタツクカウンタと、このスタツ
クカウンタの出力により上位アドレスを指定され
、サブルーチンのレベルに応じた記憶エリアが選
択される切替RAMとを具備したことを特徴とす
るマイクロプログラム制御による電子機器。
A stack RAM that sequentially stores return addresses of subroutines, a stack counter that specifies the address of this stack RAM, and an upper address is specified by the output of this stack counter, and a storage area is selected according to the level of the subroutine. An electronic device controlled by a microprogram, characterized in that it is equipped with a switching RAM.
JP7176185U 1985-05-15 1985-05-15 Expired JPH0418043Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7176185U JPH0418043Y2 (en) 1985-05-15 1985-05-15

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7176185U JPH0418043Y2 (en) 1985-05-15 1985-05-15

Publications (2)

Publication Number Publication Date
JPS61189345U true JPS61189345U (en) 1986-11-26
JPH0418043Y2 JPH0418043Y2 (en) 1992-04-22

Family

ID=30609543

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7176185U Expired JPH0418043Y2 (en) 1985-05-15 1985-05-15

Country Status (1)

Country Link
JP (1) JPH0418043Y2 (en)

Also Published As

Publication number Publication date
JPH0418043Y2 (en) 1992-04-22

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