JPS61204259U - - Google Patents

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Publication number
JPS61204259U
JPS61204259U JP8867185U JP8867185U JPS61204259U JP S61204259 U JPS61204259 U JP S61204259U JP 8867185 U JP8867185 U JP 8867185U JP 8867185 U JP8867185 U JP 8867185U JP S61204259 U JPS61204259 U JP S61204259U
Authority
JP
Japan
Prior art keywords
microprogram
control means
designation data
address control
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8867185U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8867185U priority Critical patent/JPS61204259U/ja
Publication of JPS61204259U publication Critical patent/JPS61204259U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

図面はこの考案の一実施例を示すもので、第1
図は回路構成を示すブロツク図、第2図は第1図
の切替用RAMの構成を象徴する図である。 11……ROM、111……デコーダ、12,
16,17,19……セレクタ、13……共用R
AM、14……制御部、15……切替用RAM、
18……アドレスラツチ回路18、20……演算
部20。
The drawing shows one embodiment of this invention.
The figure is a block diagram showing the circuit configuration, and FIG. 2 is a diagram symbolically showing the configuration of the switching RAM shown in FIG. 1. 11...ROM, 111...decoder, 12,
16, 17, 19...Selector, 13...Shared R
AM, 14...control unit, 15...switching RAM,
18... Address latch circuits 18, 20... Arithmetic unit 20.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] マイクロプログラムを記憶したメモリと、この
メモリの次のアドレス指定データを出力するアド
レス制御手段と、このアドレス制御手段の出力す
る上記次アドレス指定データによつてプログラム
領域に応じたRAMの記憶エリアを選択する選択
手段とを具備したことを特徴とするマイクロプロ
グラム制御による電子機器。
A memory storing a microprogram, an address control means for outputting the next address designation data of this memory, and a storage area of the RAM corresponding to the program area is selected based on the next address designation data output from the address control means. 1. An electronic device controlled by a microprogram, characterized in that it is equipped with selection means for selecting.
JP8867185U 1985-06-12 1985-06-12 Pending JPS61204259U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8867185U JPS61204259U (en) 1985-06-12 1985-06-12

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8867185U JPS61204259U (en) 1985-06-12 1985-06-12

Publications (1)

Publication Number Publication Date
JPS61204259U true JPS61204259U (en) 1986-12-23

Family

ID=30642029

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8867185U Pending JPS61204259U (en) 1985-06-12 1985-06-12

Country Status (1)

Country Link
JP (1) JPS61204259U (en)

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