JPH01135551U - - Google Patents
Info
- Publication number
- JPH01135551U JPH01135551U JP2985488U JP2985488U JPH01135551U JP H01135551 U JPH01135551 U JP H01135551U JP 2985488 U JP2985488 U JP 2985488U JP 2985488 U JP2985488 U JP 2985488U JP H01135551 U JPH01135551 U JP H01135551U
- Authority
- JP
- Japan
- Prior art keywords
- test
- signal
- input terminal
- holding means
- mode designation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 2
Description
第１図はこの考案の一実施例の回路構成を示す
ブロツク図、第２図は同実施例に用いられるテス
ト処理制御部を示す回路図である。
１…ＣＰＵ、４…ＲＯＭ、５…オペレーシヨン
デコーダ、６…ＡＬＵ、７…アドレスレジスタ、
８…汎用レジスタ、９…アドレス制御部、１０…
リセツト回路、１１…テスト処理制御部、１１１
〜１ｎ１，１１２〜１ｎ２…フリツフロツプ、２
１１〜２１ｎ…アンドゲート。
FIG. 1 is a block diagram showing the circuit configuration of an embodiment of this invention, and FIG. 2 is a circuit diagram showing a test processing control section used in the embodiment. 1...CPU, 4...ROM, 5...operation decoder, 6...ALU, 7...address register,
8...General-purpose register, 9...Address control unit, 10...
Reset circuit, 11...Test processing control section, 111
~1n1, 112~1n2...Flipflop, 2
11-21n...And gate.
Claims (1)
た中央演算装置と、入力信号が与えられる入力端
子と、上記入力端子より与えられる入力信号を保
持する信号保持手段と、この信号保持手段の状態
により対応するテストプログラムモードを指定す
るテストプログラムモード指定手段とを具備した
ことを特徴とするテストモード指定回路。 A central processing unit capable of setting a plurality of test program modes, an input terminal to which an input signal is applied, a signal holding means for holding the input signal applied from the input terminal, and a test corresponding to the state of the signal holding means. A test mode designation circuit comprising test program mode designation means for designating a program mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988029854U JPH0716188Y2 (en) | 1988-03-08 | 1988-03-08 | Test mode designation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988029854U JPH0716188Y2 (en) | 1988-03-08 | 1988-03-08 | Test mode designation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01135551U true JPH01135551U (en) | 1989-09-18 |
| JPH0716188Y2 JPH0716188Y2 (en) | 1995-04-12 |
Family
ID=31254429
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988029854U Expired - Lifetime JPH0716188Y2 (en) | 1988-03-08 | 1988-03-08 | Test mode designation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0716188Y2 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5667548U (en) * | 1979-10-25 | 1981-06-05 | ||
| JPS59146352A (en) * | 1983-02-09 | 1984-08-22 | Nec Corp | Single chip microcomputer system |
| JPS6041140A (en) * | 1983-08-16 | 1985-03-04 | Nec Corp | Debugging device of read-only memory built in semiconductor integrated circuit |
-
1988
- 1988-03-08 JP JP1988029854U patent/JPH0716188Y2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5667548U (en) * | 1979-10-25 | 1981-06-05 | ||
| JPS59146352A (en) * | 1983-02-09 | 1984-08-22 | Nec Corp | Single chip microcomputer system |
| JPS6041140A (en) * | 1983-08-16 | 1985-03-04 | Nec Corp | Debugging device of read-only memory built in semiconductor integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0716188Y2 (en) | 1995-04-12 |