JPS6262358U - - Google Patents
Info
- Publication number
- JPS6262358U JPS6262358U JP15322785U JP15322785U JPS6262358U JP S6262358 U JPS6262358 U JP S6262358U JP 15322785 U JP15322785 U JP 15322785U JP 15322785 U JP15322785 U JP 15322785U JP S6262358 U JPS6262358 U JP S6262358U
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- evaluation chip
- flop
- flip
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000011156 evaluation Methods 0.000 claims description 4
- 238000012544 monitoring process Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Debugging And Monitoring (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Description
図は本考案の実施例を示す回路図である。
主な図番の説明、1……エバリユエーシヨンチ
ツプ、2……プログラム記憶装置、3……インス
トラクシヨンデコーダ、4,5,6,7……フリ
ツプフロツプ、8……表示回路、9……イニシヤ
ル設定回路。
The figure is a circuit diagram showing an embodiment of the present invention. Explanation of main figure numbers, 1...Evaluation chip, 2...Program storage device, 3...Instruction decoder, 4, 5, 6, 7...Flip-flop, 8...Display circuit, 9... Initial setting circuit.
Claims (1)
一機能を有するエバリユエーシヨンチツプを使用
し、プログラムの評価を行うデバツグ装置に於い
て、前記エバリユエーシヨンチツプに命令コード
を与えるプログラム記憶回路と、該プログラム記
憶回路から前記エバリユエーシヨンチツプに与え
られる命令が同時に印加され、フラグのセツトあ
るいはリセツト命令を解読するインストラクシヨ
ンデコーダと、該インストラクシヨンデコーダか
ら出力されるフラグのセツト及びリセツト信号が
印加される複数のフリツプフロツプと、該フリツ
プフロツプの内容を表示する複数の表示回路とを
備え、前記フラグの状態をモニタすることを特徴
とするマイクロコンピユータのデバツグ装置。 In a debugging device that evaluates a program using an evaluation chip having substantially the same functions as a mass-produced one-chip microcomputer, the program storage circuit provides an instruction code to the evaluation chip, and the program storage circuit. an instruction decoder to which instructions given to the evaluation chip are simultaneously applied and decode flag set or reset instructions; and a plurality of instruction decoders to which flag set and reset signals output from the instruction decoder are applied. 1. A debugging device for a microcomputer, comprising: a flip-flop; and a plurality of display circuits for displaying the contents of the flip-flop, and monitoring the state of the flag.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1985153227U JPH0441392Y2 (en) | 1985-10-07 | 1985-10-07 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1985153227U JPH0441392Y2 (en) | 1985-10-07 | 1985-10-07 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6262358U true JPS6262358U (en) | 1987-04-17 |
JPH0441392Y2 JPH0441392Y2 (en) | 1992-09-29 |
Family
ID=31071919
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1985153227U Expired JPH0441392Y2 (en) | 1985-10-07 | 1985-10-07 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0441392Y2 (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55138150A (en) * | 1979-04-17 | 1980-10-28 | Toshiba Mach Co Ltd | Debugging unit of microcomputer |
JPS57152053A (en) * | 1981-03-14 | 1982-09-20 | Okuma Mach Works Ltd | Program tracing device |
JPS5829048A (en) * | 1981-08-13 | 1983-02-21 | Omron Tateisi Electronics Co | Programmable controller |
-
1985
- 1985-10-07 JP JP1985153227U patent/JPH0441392Y2/ja not_active Expired
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55138150A (en) * | 1979-04-17 | 1980-10-28 | Toshiba Mach Co Ltd | Debugging unit of microcomputer |
JPS57152053A (en) * | 1981-03-14 | 1982-09-20 | Okuma Mach Works Ltd | Program tracing device |
JPS5829048A (en) * | 1981-08-13 | 1983-02-21 | Omron Tateisi Electronics Co | Programmable controller |
Also Published As
Publication number | Publication date |
---|---|
JPH0441392Y2 (en) | 1992-09-29 |
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