JPS63151051U - - Google Patents

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Publication number
JPS63151051U
JPS63151051U JP4150787U JP4150787U JPS63151051U JP S63151051 U JPS63151051 U JP S63151051U JP 4150787 U JP4150787 U JP 4150787U JP 4150787 U JP4150787 U JP 4150787U JP S63151051 U JPS63151051 U JP S63151051U
Authority
JP
Japan
Prior art keywords
memory
data
counter
program
program counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4150787U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4150787U priority Critical patent/JPS63151051U/ja
Publication of JPS63151051U publication Critical patent/JPS63151051U/ja
Pending legal-status Critical Current

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  • Microcomputers (AREA)
  • Debugging And Monitoring (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例におけるマイクロプ
ロセツサシステムを示した構成図、第２図は上記
マイクロプロセツサに内蔵されるプログラムカウ
ンタの内部構成を示した構成図、第３図はマイク
ロプロセツサシステムに使用されるプログラム／
データメモリの状態図である。 FIG. 1 is a block diagram showing a microprocessor system according to an embodiment of the present invention, FIG. 2 is a block diagram showing the internal structure of a program counter built into the microprocessor, and FIG. Programs used in the Setsa system/
FIG. 3 is a state diagram of a data memory.

Claims (1)

【実用新案登録請求の範囲】 (1) 命令語の記憶されたアドレスを指定するプ
ログラムカウンタを有するマイクロプロセツサと
プログラム及びデータを記憶するメモリとを有す
るマイクロプロセツサシステムにおいて、 前記プログラムカウンタの最上位ビツトを「０
」又は「１」に固定し、前記メモリは、そのプロ
グラムカウンタで指定可能なメモリ領域をプログ
ラムメモリとし、他のメモリ領域をデータメモリ
としたことを特徴とするマイクロプロセツサシス
テム。 (2) 前記マイクロプロセツサはデータの記憶さ
れたアドレスを指定するデータカウンタを有し、
該データカウンタの最上位ビツトを前記プログラ
ムカウンタの最上位ビツトと反対の論理レベルに
固定したことを特徴とする実用新案登録請求の範
囲第１項記載のマイクロプロセツサシステム。[Claims for Utility Model Registration] (1) In a microprocessor system having a program counter that specifies an address where an instruction word is stored, and a memory that stores programs and data, Set the upper bit to ``0''
'' or fixed to ``1'', and the memory has a memory area that can be specified by the program counter as a program memory, and other memory areas as a data memory. (2) the microprocessor has a data counter that specifies an address where data is stored;
2. The microprocessor system according to claim 1, wherein the most significant bit of the data counter is fixed at a logic level opposite to the most significant bit of the program counter.
JP4150787U 1987-03-20 1987-03-20 Pending JPS63151051U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4150787U JPS63151051U (en) 1987-03-20 1987-03-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4150787U JPS63151051U (en) 1987-03-20 1987-03-20

Publications (1)

Publication Number Publication Date
JPS63151051U true JPS63151051U (en) 1988-10-04

Family

ID=30856577

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4150787U Pending JPS63151051U (en) 1987-03-20 1987-03-20

Country Status (1)

Country Link
JP (1) JPS63151051U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5150624A (en) * 1974-10-30 1976-05-04 Hitachi Ltd DEETASHORISOCHI
JPS52106653A (en) * 1976-03-05 1977-09-07 Hitachi Ltd Program run away prevent device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5150624A (en) * 1974-10-30 1976-05-04 Hitachi Ltd DEETASHORISOCHI
JPS52106653A (en) * 1976-03-05 1977-09-07 Hitachi Ltd Program run away prevent device

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