JPS6356447U

JPS6356447U -

Info

Publication number: JPS6356447U
Application number: JP15054386U
Authority: JP
Priority date: 1986-09-30
Filing date: 1986-09-30
Publication date: 1988-04-15

Description

[Brief explanation of the drawing]

第１図は本考案に係る装置の好適な実施例を示
すブロツク図、第２図は従来装置の構成を示すブ
ロツク図、第３図は第２図従来装置の作用を説明
するタイミングチヤート、第４図は第１図実施例
の作用を説明するタイミングチヤートである。１０……タイミングコントローラ、１２……プ
ログラムカウンタ、１４……マイクロプログラム
メモリ、１６―１，１６―２……数値メモリ、１
８……演算プロセツサ、２２……演算値メモリ、
２４……アドレスラツチ。 Fig. 1 is a block diagram showing a preferred embodiment of the device according to the present invention, Fig. 2 is a block diagram showing the configuration of a conventional device, and Fig. 3 is a timing chart explaining the operation of the conventional device shown in Fig. 2. FIG. 4 is a timing chart explaining the operation of the embodiment shown in FIG. 10... Timing controller, 12... Program counter, 14... Micro program memory, 16-1, 16-2... Numerical memory, 1
8... Arithmetic processor, 22... Arithmetic value memory,
24...Address latch.

Claims

[Claims for Utility Model Registration] A microprogram memory from which a numeric read address and a calculated value write address are read from an address specified by a program counter; a numeric memory from which a numeric value is read from the numeric read address; and the calculated value. An address latch that temporarily holds a write address, an arithmetic processor that performs an operation using the numerical value read from the numerical memory, and an arithmetic value that writes the arithmetic value of the arithmetic processor to the address held in the address latch. An arithmetic device comprising: a memory;